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* cpus: Have cpu_exec_initfn() per user / system emulationPhilippe Mathieu-Daudé2025-03-062-0/+12
| | | | | | | | | Slighly simplify cpu-target.c again by extracting cpu_exec_initfn() to cpu-{system,user}.c, adding an empty stub for user emulation. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-19-philmd@linaro.org>
* cpus: Have cpu_class_init_props() per user / system emulationPhilippe Mathieu-Daudé2025-03-063-1/+71
| | | | | | | | | | Rather than maintaining a mix of system / user code for CPU class properties, move system properties to cpu-system.c and user ones to the new cpu-user.c unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-18-philmd@linaro.org>
* accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | | | TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-11-philmd@linaro.org>
* accel/tcg: Remove pointless initialization of cflags_next_tbPhilippe Mathieu-Daudé2025-03-061-1/+0
| | | | | | | | | | cflags_next_tb is always re-initialized in the CPU Reset() handler in cpu_common_reset_hold(), no need to initialize it in cpu_common_initfn(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-13-philmd@linaro.org>
* cpus: Keep default fields initialization in cpu_common_initfn()Philippe Mathieu-Daudé2025-03-061-0/+2
| | | | | | | | | | | | cpu_common_initfn() is our target agnostic initializer, while cpu_exec_initfn() is the target specific one. The %as and %num_ases fields are not target specific, so initialize them in the common helper. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-6-philmd@linaro.org>
* cpus: Cache CPUClass early in instance_init() handlerPhilippe Mathieu-Daudé2025-03-061-0/+3
| | | | | | | | | Cache CPUClass as early as possible, when the instance is initialized. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-5-philmd@linaro.org>
* Merge tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi2025-03-056-43/+457
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ8ezJgAKCRAfewwSUazn # 0T9pAQCKb+C69kbf9cEVg7PU/z5I0ALFtCNWCKxSkWZPDPik4gEA3IYwdrJ+csuX # 8nWL0fzyk+8+LDzEwEgCYoNcMnttRQw= # =P8mi # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 10:12:54 HKT # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250305' of https://gitlab.com/bibo-mao/qemu: target/loongarch: Adjust the cpu reset action to a proper position hw/loongarch/virt: Enable cpu hotplug feature on virt machine hw/loongarch/virt: Update the ACPI table for hotplug cpu hw/loongarch/virt: Implement cpu plug interface hw/loongarch/virt: Implement cpu unplug interface hw/loongarch/virt: Add basic cpu plug interface framework hw/loongarch/virt: Add topo properties on CPU object hw/loongarch/virt: Add CPU topology support hw/intc/loongarch_extioi: Use cpu plug notification hw/intc/loongarch_extioi: Implment cpu hotplug interface hw/intc/loongarch_extioi: Add basic hotplug framework hw/intc/loongarch_extioi: Move gpio irq initial to common code hw/intc/loongarch_ipi: Notify ipi object when cpu is plugged hw/intc/loongarch_ipi: Implment cpu hotplug interface hw/intc/loongarch_ipi: Add basic hotplug framework Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * hw/loongarch/virt: Enable cpu hotplug feature on virt machineBibo Mao2025-03-051-2/+42
| | | | | | | | | | | | | | | | | | | | On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs, there is socket-id/core-id/thread-id property set, arch_id can be caculated from these properties. So that cpu slot can be searched from its arch_id. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/loongarch/virt: Update the ACPI table for hotplug cpuBibo Mao2025-03-053-3/+43
| | | | | | | | | | | | | | | | | | On LoongArch virt machine, ACPI GED hardware is used for CPU hotplug handler, here CPU hotplug support feature is added based on GED handler, also CPU scan and reject method is added about CPU device in DSDT table. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/loongarch/virt: Implement cpu plug interfaceBibo Mao2025-03-051-11/+77
| | | | | | | | | | | | | | | | Implement cpu plug interface, and cold-plug cpu uses plug interface when cpu object is created. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/loongarch/virt: Implement cpu unplug interfaceBibo Mao2025-03-051-0/+58
| | | | | | | | | | | | | | | | Implement cpu unplug interfaces including virt_cpu_unplug_request() and virt_cpu_unplug(). Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/loongarch/virt: Add basic cpu plug interface frameworkBibo Mao2025-03-051-0/+29
| | | | | | | | | | | | | | | | Add basic cpu hotplug interface framework, cpu hotplug interface is stub function and only framework is added here. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/loongarch/virt: Add CPU topology supportBibo Mao2025-03-051-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | Add topological relationships for Loongarch VCPU and initialize topology member variables. On LoongArch system there is socket/core/thread topo information, physical CPU id is calculated from CPU topo, every topo sub-field is aligned by power of 2. So it is different from logical cpu index. Co-developed-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_extioi: Use cpu plug notificationBibo Mao2025-03-051-10/+2
| | | | | | | | | | | | | | | | Use hotplug_handler_plug() to nofity extioi object when cold-plug cpu is created, so that extioi can set and configure irq routing to new cpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_extioi: Implment cpu hotplug interfaceBibo Mao2025-03-051-0/+45
| | | | | | | | | | | | When cpu is added, connect extioi gpio irq to CPU irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_extioi: Add basic hotplug frameworkBibo Mao2025-03-051-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | LoongArch extioi interrupt controller routes peripheral interrupt to multiple CPUs, physical cpu id is used in interrupt routing table. Here hotplug interface is added for extioi object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_extioi: Move gpio irq initial to common codeBibo Mao2025-03-052-8/+6
| | | | | | | | | | | | | | | | When cpu is added, it will connect gpio irq line to cpu irq. And cpu hot-add is put in common code, move gpio irq initial part into common code. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_ipi: Notify ipi object when cpu is pluggedBibo Mao2025-03-051-3/+2
| | | | | | | | | | | | | | | | Use hotplug_handler_plug() to nofity ipi object when cold-plug cpu is created, so that ipi can set and configure irq routing to new cpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_ipi: Implment cpu hotplug interfaceBibo Mao2025-03-051-0/+39
| | | | | | | | | | | | | | Add logic cpu allocation and cpu mapping with cpu hotplug interface. When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
| * hw/intc/loongarch_ipi: Add basic hotplug frameworkBibo Mao2025-03-051-0/+32
| | | | | | | | | | | | | | | | | | | | | | LoongArch ipi can send interrupt to multiple CPUs, interrupt routing to CPU comes from destination physical cpu id. Here hotplug interface is added for IPI object, so that parent irq line can be connected, and routing table can be added for new created cpu. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao <maobibo@loongson.cn>
* | Merge tag 'pull-riscv-to-apply-20250305-1' of ↵Stefan Hajnoczi2025-03-0511-124/+697
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/alistair23/qemu into staging Third RISC-V PR for 10.0 * CSR coverity fixes * Fix unexpected behavior of vector reduction instructions when vl is 0 * Fix incorrect vlen comparison in prop_vlen_set * Throw debug exception before page fault * Remove redundant "hart_idx" masking from APLIC * Add support for Control Transfer Records Ext * Remove redundant struct members from the IOMMU * Remove duplicate definitions from the IOMMU * Fix tick_offset migration for Goldfish RTC * Add serial alias in virt machine DTB * Remove Bin Meng from RISC-V maintainers * Add support for Control Transfer Records Ext * Log guest errors when reserved bits are set in PTEs * Add missing Sdtrig disas CSRs * Correct the hpmevent sscofpmf mask * Mask upper sscofpmf bits during validation * Remove warnings about Smdbltrp/Smrnmi being disabled * Respect mseccfg.RLB bit for TOR mode PMP entry * Update KVM support to Linux 6.14-rc3 * IOMMU HPM support * Support Sscofpmf/Svade/Svadu/Smnpm/Ssnpm extensions in KVM * Add --ignore-family option to binfmt * Refinement for AIA with KVM acceleration * Reset time changes for KVM # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmfHrkEACgkQr3yVEwxT # gBNGTA/+N9nBPZt5cv0E/0EDZMQS8RQrQvz1yHRgAXOq8RnOdcL72v8wovGAfnVu # l0BXDoVBvw4f2Xm9Q4ptlfH8HAefCeQ4E/K9j5Lwxr8OqZHFg6e+JQIyZOt6wBWI # hJbz1/laJIbXq3cGgwcE/l0aGfb2UAAsA4dsZVt/MnjAV8GS7BF9RCkgCPxD4FZA # 0PLiq9dF+4o4q7PxnxAbUVz/uhLzqmcnQemQFHbf9Wms3tZEDKmPSoKP/v+01Rkw # tm+cgy7OocpgygbMc0nykYG50P+raUBSesk/jFGeKj8cU4IeMuzDsVPWcd4rG+0X # Z+nENfOY7vOqMCXgaQCW2r4vEQx2Gj0yQG6xmVAemRWzFHJdz5W01/uUSHzJSB+L # +VbAH55HYKr6sbgecqInQ/rsHKyw6D5QFcj/guz+kvhsH9rJ5q60uywrWL5OEuaK # vKv7cSZghlf9bwy6soassXxk8z+j4psJ7WnnVpynNKMew9yFFDhayuIFbo9952gH # 3+NCm2cQrkTYJOXAJwkxBD+I4AXxNSuxNjaVANk9q80uqbT9JiHM7pcvbJI00Fji # OutJSPYtVXEin9Ev3sJ05YQHsIcZ/Noi3O5IdaRI0AMk/8gyGyhFCVgSpV52dH59 # HguPK05e5cW/xgElGUPHrU+UtzE05p18HnSoVPclF/B5rc8QXN0= # =dobk # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:52:01 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250305-1' of https://github.com/alistair23/qemu: (59 commits) target/riscv/kvm: add missing KVM CSRs target/riscv/kvm: add kvm_riscv_reset_regs_csr() target/riscv/cpu: remove unneeded !kvm_enabled() check hw/intc/aplic: refine kvm_msicfgaddr hw/intc/aplic: refine the APLIC realize hw/intc/imsic: refine the IMSIC realize binfmt: Add --ignore-family option binfmt: Normalize host CPU architecture binfmt: Shuffle things around target/riscv/kvm: Add some exts support docs/specs/riscv-iommu.rst: add HPM support info hw/riscv: add IOMMU HPM trace events hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap hw/riscv/riscv-iommu: add hpm events mmio write hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes hw/riscv/riscv-iommu: instantiate hpm_timer hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr() hw/riscv/riscv-iommu: add riscv-iommu-hpm file hw/riscv/riscv-iommu-bits.h: HPM bits ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | hw/intc/aplic: refine kvm_msicfgaddrYong-Xuan Wang2025-03-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let kvm_msicfgaddr use the same format with mmsicfgaddr and smsicfgaddr. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-4-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/aplic: refine the APLIC realizeYong-Xuan Wang2025-03-041-23/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the APLIC is emulated in the kernel, the GPIO output lines to CPUs can be remove. In this case the APLIC trigger CPU interrupts by KVM APIs. This patch also move the code that claim the CPU interrupts to the beginning of APLIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-3-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/imsic: refine the IMSIC realizeYong-Xuan Wang2025-03-041-21/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the IMSIC is emulated in the kernel, the GPIO output lines to CPUs and aia_ireg_rmw_fn setting can be remove. In this case the IMSIC trigger CPU interrupts by KVM APIs, and the RMW of IREG is handled in kernel. This patch also move the code that claim the CPU interrupts to the beginning of IMSIC realization. This can avoid the unnecessary resource allocation before checking failed. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250224025722.3999-2-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv: add IOMMU HPM trace eventsDaniel Henrique Barboza2025-03-042-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a handful of trace events to allow for an easier time debugging the HPM feature. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM capTomasz Jeznach2025-03-041-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have every piece in place we can advertise CAP_HTM to software, allowing any HPM aware driver to make use of the counters. HPM is enabled/disabled via the 'hpm-counters' attribute. Default value is 31, max value is also 31. Setting it to zero will disable HPM support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add hpm events mmio writeTomasz Jeznach2025-03-044-1/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support hpm events mmio writes, done via riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters' IOMMU property that are used to determine the amount of counters available in the IOMMU. Note that everything we did so far didn't change any IOMMU behavior because we're still not advertising HPM capability to software. This will be done in the next patch. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add IOHPMCYCLES mmio writeTomasz Jeznach2025-03-043-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISCV_IOMMU_REG_IOHPMCYCLES writes are done by riscv_iommu_process_hpmcycle_write(), called by the mmio write callback via riscv_iommu_process_hpm_writes(). Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add IOCOUNTINH mmio writesTomasz Jeznach2025-03-043-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(), which is called during riscv_iommu_mmio_write() callback via a new riscv_iommu_pricess_hpm_writes() helper. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: instantiate hpm_timerTomasz Jeznach2025-03-044-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next HPM related changes requires the HPM overflow timer to be initialized by the riscv-iommu base emulation. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()Tomasz Jeznach2025-03-044-15/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will increment a specific counter, generating an interrupt when an overflow occurs. Some extra changes in riscv-iommu.c were required to add this new helper in riscv-iommu-hpm.c: - RISCVIOMMUContext was moved to riscv-iommu.h, making it visible in riscv-iommu-hpm.c; - riscv_iommu_notify() is now public. No behavior change is made since HPM support is not being advertised yet. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: add riscv-iommu-hpm fileTomasz Jeznach2025-03-045-2/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HPM (Hardware Performance Monitor) support consists of almost 7 hundred lines that would be put on top of the base riscv-iommu emulation. To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file that will contain HPM specific code. We'll start by adding riscv_iommu_hpmcycle_read(), a helper that will be called during the riscv_iommu_mmio_read() callback. This change will have no effect on the existing emulation since we're not declaring HPM feature support. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu-bits.h: HPM bitsTomasz Jeznach2025-03-041-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the relevant HPM (High Performance Monitor) bits that we'll be using in the next patches. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu.h: add missing headersDaniel Henrique Barboza2025-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header is incomplete, i.e. it is using definitions that are being supplied by the .c files that are including it. Adding this header into a fresh .c file will result in errors: /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:30:17: error: field ‘parent_obj’ has incomplete type 30 | DeviceState parent_obj; | ^~~~~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:50:5: error: unknown type name ‘dma_addr_t’; did you mean ‘in_addr_t’? 50 | dma_addr_t cq_addr; /* Command queue base physical address */ | ^~~~~~~~~~ | in_addr_t (...) /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:62:5: error: unknown type name ‘QemuThread’; did you mean ‘GThread’? 62 | QemuThread core_proc; /* Background processing thread */ | ^~~~~~~~~~ | GThread /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:63:5: error: unknown type name ‘QemuCond’ 63 | QemuCond core_cond; /* Background processing wake up signal */ | ^~~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:71:18: error: field ‘trap_as’ has incomplete type 71 | AddressSpace trap_as; | ^~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:72:18: error: field ‘trap_mr’ has incomplete type 72 | MemoryRegion trap_mr; | ^~~~~~~ /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:80:18: error: field ‘regs_mr’ has incomplete type 80 | MemoryRegion regs_mr; | ^~~~~~~ Fix it by adding the missing headers for these definitions. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250224190826.1858473-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/virt: Add serial alias in DTBVasilis Liaskovitis2025-03-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an "aliases" node with a "serial0" entry for the single UART in the riscv virt machine. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2774 Signed-off-by: Vasilis Liaskovitis <vliaskovitis@suse.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250116161007.39710-1-vliaskovitis@suse.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | goldfish_rtc: Fix tick_offset migrationRodrigo Dias Correa2025-03-041-30/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of migrating the raw tick_offset, goldfish_rtc migrates a recalculated value based on QEMU_CLOCK_VIRTUAL. As QEMU_CLOCK_VIRTUAL stands still across a save-and-restore cycle, the guest RTC becomes out of sync with the host RTC when the VM is restored. As described in the bug description, it looks like this calculation was copied from pl031 RTC, which had its tick_offset migration fixed by Commit 032cfe6a79c8 ("pl031: Correctly migrate state when using -rtc clock=host"). Migrate the tick_offset directly, adding it as a version-dependent field to VMState. Keep the old behavior when migrating from previous versions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2033 Signed-off-by: Rodrigo Dias Correa <r@drigo.nl> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250114212150.228241-1-r@drigo.nl> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu-bits: Remove duplicate definitionsJason Chien2025-03-041-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header contains duplicate macro definitions. This commit eliminates the duplicate part. Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250115141730.30858-2-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/riscv/riscv-iommu: Remove redundant struct membersJason Chien2025-03-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initially, the IOMMU would create a thread, but this thread was removed in the merged version. The struct members for thread control should have been removed as well, but they were not removed in commit 0c54acb8243 ("hw/riscv: add RISC-V IOMMU base emulation"). Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250115141730.30858-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| * | hw/intc/riscv_aplic: Remove redundant "hart_idx" maskingHuang Borong2025-03-041-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the redundant masking of "hart_idx", as the same operation is performed later during address calculation. This change impacts the "hart_idx" value in the final qemu_log_mask() call. The original "hart_idx" parameter should be used for logging to ensure accuracy, rather than the masked value. Signed-off-by: Huang Borong <huangborong@bosc.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20250115035105.19600-1-huangborong@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* | Merge tag 'hw-misc-20250305' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-03-0547-183/+2337
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Misc HW patches - Remove TCG dependency on ARM_GICV3 (Philippe) - Add MMIO interface to PVPanic device (Alexander) - Add vmapple machine (Alexander & Phil) - Restrict part of sPAPR PAGE_INIT hypercall to TCG (Philippe) - Make ghes_record_cper_errors() scope static (Gavin) - Do not expose the ARM virt machines on Xen-only binary (Philippe) - Xen header cleanups (Philippe) - Set Freescale eTSEC network device description & category (Zoltan) - Improve RX FIFO depth for various UARTs (Philippe) - Prevent TX FIFO memory leak in SiFive UART (Alistair) - Cleanups in MacIO and AT24C EEPROM (Zoltan) - Add UFS temperature event notification support & test (Keoseong) - Remove printf() calls in hw/arm/ (Peter) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfHpagACgkQ4+MsLN6t # wN4dTg//Z2neoENdnZglRp6q66LLxSTHJnHUMNHe2Bp+KKfhce+//j+CFYgOnJjV # P5eExzvHvtYFL6lNXOR7MTM/i/4pixcLYh8anyrnUWkEiufGXI4/30QePbwAAdkZ # kQ1CpLI43ZdnMLTh18JswLo/JMkl/jJGvCGNjhtQVnobqam+ATgAbjmcnwA8esJS # cCQVFzno9TNvsCnUtMe3IdOfIs9K3atCARbXpA3i3wd52P+NHvGO1jU0QPFBm2Lr # 4kcFLI1Sg2vYWD3FujDPeCcfI7kcRDIjHS6vVplK1VlCjjdaQmxx6XKO72PnZZOG # 7sra8xJpW8mZS2jfN2AxKMVlNndZMYzAJoS2UBMp1YX8KBEzlcmI2uSjGas6bcmQ # XIaP7/mggx7yBU3nspUl8rqY/3Z3wVjwepf1l8KOn9Z13wo+APv4aj6W+zkK96A5 # NGq6EpoKquINGLBBMkZAdfBOKk97NhwHh1Op04VgJNnPESpLnb5hENtZW1ksg92r # tijWdDWnC/JtWMU2dAnmT/9Vaxk4fukGqqncXqQJzGBw0OylzWh5b2Zer02WFyxz # oplISEwU3uFcg0OLa9aUHgs7lVWBUbEW3pSk1CtKuqgPtwxm/Gr2KbAVgAbFiyzr # 6YPQsfFP5z6CjreOWMELPWmsYV+jtTj/KoIek2QlYt7Ex6uiA6c= # =TcY9 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:15:20 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250305' of https://github.com/philmd/qemu: (41 commits) hw/nvram/eeprom_at24c: Reorganise init to avoid overwriting values hw/nvram/eeprom_at24c: Remove memset after g_malloc0 hw/nvram/eeprom_at24c: Remove ERR macro that calls fprintf to stderr hw/nvram/eeprom_at24c: Use OBJECT_DECLARE_SIMPLE_TYPE hw/arm/versatilepb: Convert printfs to LOG_GUEST_ERROR hw/arm/omap_sx1: Remove ifdeffed out debug printf hw/arm/omap1: Convert information printfs to tracepoints hw/arm/omap1: Drop ALMDEBUG ifdeffed out code hw/arm/omap1: Convert raw printfs to qemu_log_mask() tests/qtest/ufs-test: Add test code for the temperature feature hw/ufs: Add temperature event notification support hw/misc/macio/gpio: Add constants for register bits hw/misc/macio: Improve trace logs hw/char/sifive_uart: Free fifo on unrealize hw/char/sh_serial: Return correct number of empty RX FIFO elements hw/char/mcf_uart: Really use RX FIFO depth hw/char/mcf_uart: Use FIFO_DEPTH definition instead of magic values hw/char/imx_serial: Really use RX FIFO depth hw/char/bcm2835_aux: Really use RX FIFO depth hw/char/pl011: Really use RX FIFO depth ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | hw/nvram/eeprom_at24c: Reorganise init to avoid overwriting valuesBALATON Zoltan2025-03-051-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The init_rom[] can write values to the beginning of the memory but these are overwritten by values from a backing file that covers the whole memory. init_rom[] is used only if there's no backing file (provides default content) but should not overwrite backing file content (especially leaving the file unchanged and only change it in memory). Do the init_rom[] handling only if it would not be overwritten. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <fd8e0478febd60d5f48c58bc77c60e043d1c3cdc.1740839457.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/nvram/eeprom_at24c: Remove memset after g_malloc0BALATON Zoltan2025-03-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling memset to zero memory is not needed after g_malloc0 which already clears memory. These used to be in separate functions but after some patches the memset ended up after g_malloc0 and thus can be dropped. Fixes: 4f2c6448c3 (hw/nvram/eeprom_at24c: Make reset behavior more like hardware) Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <ff281851e6d824ecd01b8b5cd955328dae1515a0.1740839457.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/nvram/eeprom_at24c: Remove ERR macro that calls fprintf to stderrBALATON Zoltan2025-03-051-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the realize method error_setg can be used like other places there already do. The other usage can be replaced with error_report which is the preferred way instead of directly printing to stderr. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <637b92984795a385b648a84208f093947cc261e4.1740839457.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/nvram/eeprom_at24c: Use OBJECT_DECLARE_SIMPLE_TYPEBALATON Zoltan2025-03-051-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | No need to open code it so use the simple object type declaration. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <08d9900af04789ede485942c8072eaa58bf52f80.1740839457.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/arm/versatilepb: Convert printfs to LOG_GUEST_ERRORPeter Maydell2025-03-051-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert some printf() calls for attempts to access nonexistent registers into LOG_GUEST_ERROR logging. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250227170117.1726895-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/arm/omap_sx1: Remove ifdeffed out debug printfPeter Maydell2025-03-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove an ifdeffed out debug printf from the static_write() function in omap_sx1.c. In theory we could turn this into a tracepoint, but for code this old it doesn't seem worthwhile. We can add tracepoints if and when we have a reason to debug something. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250227170117.1726895-5-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/arm/omap1: Convert information printfs to tracepointsPeter Maydell2025-03-052-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap1 code uses raw printf() statements to print information about some events; convert these to tracepoints. In particular, this will stop the functional test for the sx1 from printing the not-very-helpful note "omap_clkm_write: clocking scheme set to synchronous scalable" to the test's default.log. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250227170117.1726895-4-peter.maydell@linaro.org> [PMD: Include component name (pwl/pwt/lpg) in trace events] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/arm/omap1: Drop ALMDEBUG ifdeffed out codePeter Maydell2025-03-051-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In omap1.c, there are some debug printfs in the omap_rtc_write() function that are guardad by ifdef ALMDEBUG. ALMDEBUG is never set, so this is all dead code. It's not worth the effort of converting all of these to tracepoints; a modern tracepoint approach would probably have a single tracepoint covering all the register writes anyway. Just delete the printf()s. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250227170117.1726895-3-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/arm/omap1: Convert raw printfs to qemu_log_mask()Peter Maydell2025-03-051-17/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap1.c is very old code, and it contains numerous calls direct to printf() for various error and information cases. In this commit, convert the printf() calls that are for either guest error or unimplemented functionality to qemu_log_mask() calls. This leaves the printf() calls that are informative or which are ifdeffed-out debug statements untouched. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250227170117.1726895-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| * | hw/ufs: Add temperature event notification supportKeoseong Park2025-03-052-1/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces temperature event notification support to the UFS emulation. It enables the emulated UFS device to generate temperature-related events, including high and low temperature notifications, in compliance with the UFS specification. With this feature, UFS drivers can now handle temperature exception events during testing and development within the emulated environment. This enhances validation and debugging capabilities for thermal event handling in UFS implementations. Signed-off-by: Keoseong Park <keosung.park@samsung.com> Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com> Message-ID: <20250225064146epcms2p50889cb0066e2d4734f2386de325bcdf6@epcms2p5> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>