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* | hw/arm/aspeed: use qemu_configure_nic_device()David Woodhouse2024-02-021-5/+4
| | | | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Acked-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org>
* | hw/arm/allwinner: use qemu_configure_nic_device()David Woodhouse2024-02-023-35/+4
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/xtensa/virt: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/sparc64/sun4u: use pci_init_nic_devices()David Woodhouse2024-02-021-19/+8
| | | | | | | | | | | | | | | | | | | | | | The first sunhme NIC gets placed a function 1 on slot 1 of PCI bus A, and the rest are dynamically assigned on PCI bus B. Previously, any PCI NIC would get the special treatment purely by virtue of being first in the list. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/sh4/r2d: use pci_init_nic_devices()David Woodhouse2024-02-021-4/+2
| | | | | | | | | | | | | | | | | | | | | | Previously, the first PCI NIC would be assigned to slot 2 even if the user override the model and made it something other than an rtl8139 which is the default. Everything else would be dynamically assigned. Now, the first rtl8139 gets slot 2 and everything else is dynamic. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
* | hw/ppc: use pci_init_nic_devices()David Woodhouse2024-02-024-18/+8
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/ppc/spapr: use qemu_get_nic_info() and pci_init_nic_devices()David Woodhouse2024-02-021-13/+5
| | | | | | | | | | | | | | | | | | | | | | Avoid directly referencing nd_table[] by first instantiating any spapr-vlan devices using a qemu_get_nic_info() loop, then calling pci_init_nic_devices() to do the rest. No functional change intended. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/ppc/prep: use pci_init_nic_devices()David Woodhouse2024-02-021-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the first PCI NIC would be placed in PCI slot 3 and the rest would be dynamically assigned. Even if the user overrode the default NIC type and made it something other than PCNet. Now, the first PCNet NIC (that is, anything not explicitly specified to be anything different) will go to slot 3 even if it isn't the first NIC specified on the command line. And anything else will be dynamically assigned. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/mips/loongson3_virt: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/mips/malta: use pci_init_nic_devices()David Woodhouse2024-02-021-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | The Malta board setup code would previously place the first NIC into PCI slot 11 if was a PCNet card, and the rest (including the first if it was anything other than a PCNet card) would be dynamically assigned. Now it will place any PCNet NIC into slot 11, and then anything else will be dynamically assigned. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/mips/fuloong2e: use pci_init_nic_devices()David Woodhouse2024-02-021-13/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous behaviour was: *if* the first NIC specified on the command line was an RTL8139 (or unspecified model) then it gets assigned to PCI slot 7, which is where the Fuloong board had an RTL8139. All other devices (including the first, if it was specified as anything other than an rtl8319) get dynamically assigned on the bus. The new behaviour is subtly different: If the first NIC was given a specific model *other* than rtl8139, and a subsequent NIC was not, then the rtl8139 (or unspecified) NIC will go to slot 7 and the rest will be dynamically assigned. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/loongarch: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Song Gao <gaosong@loongson.cn>
* | hw/hppa: use pci_init_nic_devices()David Woodhouse2024-02-021-5/+2
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/virt: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/sbsa-ref: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* | hw/alpha/dp264: use pci_init_nic_devices()David Woodhouse2024-02-021-3/+1
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/xen: use qemu_create_nic_bus_devices() to instantiate Xen NICsDavid Woodhouse2024-02-026-49/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When instantiating XenBus itself, for each NIC which is configured with either the model unspecified, or set to to "xen" or "xen-net-device", create a corresponding xen-net-device for it. Now we can revert the previous more hackish version which relied on the platform code explicitly registering the NICs on its own XenBus, having returned the BusState* from xen_bus_init() itself. This also fixes the setup for Xen PV guests, which was previously broken in various ways and never actually managed to peer with the netdev. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
* | hw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()David Woodhouse2024-02-021-12/+19
| | | | | | | | | | | | | | | | | | Eliminate direct access to nd_table[] and nb_nics by processing the the Xen and ISA NICs first and then calling pci_init_nic_devices() for the rest. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
* | hw/pci: add pci_init_nic_devices(), pci_init_nic_in_slot()David Woodhouse2024-02-021-0/+45
|/ | | | | | | | | | | | The loop over nd_table[] to add PCI NICs is repeated in quite a few places. Add a helper function to do it. Some platforms also try to instantiate a specific model in a specific slot, to match the real hardware. Add pci_init_nic_in_slot() for that purpose. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
* Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into ↵Peter Maydell2024-02-0117-48/+1031
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Hook up FSI module in AST2600Ninad Palsule2024-02-011-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patchset introduces IBM's Flexible Service Interface(FSI). Time for some fun with inter-processor buses. FSI allows a service processor access to the internal buses of a host POWER processor to perform configuration or debugging. FSI has long existed in POWER processes and so comes with some baggage, including how it has been integrated into the ASPEED SoC. Working backwards from the POWER processor, the fundamental pieces of interest for the implementation are: 1. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on buses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block. 2. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached. 3. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM. 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The implementation appears as following in the qemu device tree: (qemu) info qtree bus: main-system-bus type System ... dev: aspeed.apb2opb, id "" gpio-out "sysbus-irq" 1 mmio 000000001e79b000/0000000000001000 bus: opb.1 type opb dev: fsi.master, id "" bus: fsi.bus.1 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.1 type lbus dev: scratchpad, id "" address = 0 (0x0) bus: opb.0 type opb dev: fsi.master, id "" bus: fsi.bus.0 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.0 type lbus dev: scratchpad, id "" address = 0 (0x0) The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are attached to the CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the 'config' member of LBusDeviceClass to match the engine's type. CFAM designs offer a lot of flexibility, for instance it is possible for a CFAM to be simultaneously driven from multiple FSI links. The modeling is not so complete; it's assumed that each CFAM is attached to a single FSI slave (as a consequence the CFAM subclasses the FSI slave). As for FSI, its symbols and wire-protocol are not modelled at all. This is not necessary to get FSI off the ground thanks to the mapping of the CFAM address space onto the OPB address space - the models follow this directly and map the CFAM memory region into the OPB's memory region. Future work includes supporting more advanced accesses that drive the FSI master directly rather than indirectly via the CFAM mapping, which will require implementing the FSI state machine and methods for each of the FSI symbols on the slave. Further down the track we can also look at supporting the bitbanged SoftFSI drivers in Linux by extending the FSI slave model to resolve sequences of GPIO IRQs into FSI symbols, and calling the associated symbol method on the slave to map the access onto the CFAM. Testing: Tested by reading cfam config address 0 on rainier machine type. root@p10bmc:~# pdbg -a getcfam 0x0 p0: 0x0 = 0xc0022d15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Aspeed APB2OPB & On-chip peripheral busNinad Palsule2024-02-015-0/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved FSIMasterState under AspeedAPB2OPBState - modified fsi_opb_fsi_master_address() and fsi_opb_opb2fsi_address() - instroduced fsi_aspeed_apb2opb_init() - reworked fsi_aspeed_apb2opb_realize() - removed FSIMasterState object and fsi_opb_realize() - simplified OPBus - introduced fsi_aspeed_apb2opb_rw to fix endianness issue ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's FSI masterNinad Palsule2024-02-013-1/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - move FSICFAMState object under FSIMasterState - introduced fsi_master_init() - reworked fsi_master_realize() - dropped FSIBus definition ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's cfamNinad Palsule2024-02-013-1/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved object FSIScratchPad under FSICFAMState - moved FSIScratchPad code under cfam.c - introduced fsi_cfam_instance_init() - reworked fsi_cfam_realize() ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's fsi-slave modelNinad Palsule2024-02-012-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's FSI BusNinad Palsule2024-02-012-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where FSI bus is introduced. The FSI bus is a simple bus where FSI master is attached. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - removed include/hw/fsi/engine-scratchpad.h and hw/fsi/engine-scratchpad.c - dropped FSI_SCRATCHPAD - included FSIBus definition - dropped hw/fsi/trace-events changes ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's scratchpad deviceNinad Palsule2024-02-012-2/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. The scratchpad provides a set of non-functional registers. The firmware is free to use them, hardware does not support any special management support. The scratchpad registers can be read or written from LBUS slave. The scratch pad is managed under FSI CFAM state. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved object FSIScratchPad under FSICFAMState - moved FSIScratchPad code under cfam.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/fsi: Introduce IBM's Local busNinad Palsule2024-02-017-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a part of patchset where IBM's Flexible Service Interface is introduced. The LBUS is modelled to maintain mapped memory for the devices. The memory is mapped after CFAM config, peek table and FSI slave registers. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - removed lbus_add_device() bc unused - removed lbus_create_device() bc used only once - removed "address" property - updated meson.build to build fsi dir - included an empty hw/fsi/trace-events ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé2024-02-015-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helperPhilippe Mathieu-Daudé2024-02-014-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | In order to alter AspeedSoCClass::cpu_type in the next commit, introduce the aspeed_soc_cpu_type() helper to retrieve the per-SoC CPU type from AspeedSoCClass. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Init CPU defaults in a common helperPhilippe Mathieu-Daudé2024-02-011-43/+28
| | | | | | | | | | | | | | | | | | | | | | Rework aspeed_soc_num_cpus() as a new init_cpus_defaults() helper to reduce code duplication. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus()Philippe Mathieu-Daudé2024-02-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit b7f1a0cb76 ("arm/aspeed: Compute the number of CPUs from the SoC definition") Aspeed machines use the aspeed_soc_num_cpus() helper to set the number of CPUs. Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc: Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
| * hw/arm/aspeed: Remove dead codePhilippe Mathieu-Daudé2024-02-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed: Adding new machine Tiogapass in QEMU"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingPeter Maydell2024-01-3116-11/+16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | trivial patches for 2024-01-31 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmW6NScPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZdQYH/2fhfhZotH0V2qAcMxlOoHbAE9UhZNRsSYtf # QFP0GXFYFAMm7LHkPUbvKgO7LylKWAOMn/zKZqgj1Vf1EpoKQ2FwLtR/buDz86Ec # pi2OrDPRA7Ay5c3ow3YZZkUOhQTTcR5rNjYctPtt/J4j8ol/z5vre7weJIg2bCJe # zI7vIVg7iFFzbkXY20KHngJ5nDC+aEm7WaGlxAP8kfkvy324Wy9O2k8qu2J5zbLT # HGvh3rwEDvRTYe4CaKFFHWNV0m4092HAr/dJBobugI5VZ6QQpK6Tgy8N+4ZrCHD2 # SjUKeym85VTOYGuY8b18fk5MQK2SzsfBUJ4x8VGC75W4mJ8agdc= # =HImO # -----END PGP SIGNATURE----- # gpg: Signature made Wed 31 Jan 2024 11:55:19 GMT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) hw/hyperv: Include missing headers hw/intc/xics: Include missing 'cpu.h' header hw/arm: Add `\n` to hint message hw/loongarch: Add `\n` to hint message hw/i386: Add `\n` to hint message backends/hostmem: Fix block comments style (checkpatch.pl warnings) misc: Clean up includes riscv: Clean up includes cxl: Clean up includes include: Clean up includes m68k: Clean up includes acpi: Clean up includes aspeed: Clean up includes disas/riscv: Clean up includes hyperv: Clean up includes scripts/clean-includes: Update exclude list mailmap: Fix Stefan Weil email qemu-docs: Update options for graphical frontends qapi/migration.json: Fix the member name for MigrationCapability colo: examples: remove mentions of script= and (wrong) downscript= ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/hyperv: Include missing headersPhilippe Mathieu-Daudé2024-01-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include missing headers in order to avoid when refactoring unrelated headers: hw/hyperv/hyperv.c:33:18: error: field ‘msg_page_mr’ has incomplete type 33 | MemoryRegion msg_page_mr; | ^~~~~~~~~~~ hw/hyperv/hyperv.c: In function ‘synic_update’: hw/hyperv/hyperv.c:64:13: error: implicit declaration of function ‘memory_region_del_subregion’ [-Werror=implicit-function-declaration] 64 | memory_region_del_subregion(get_system_memory(), | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ hw/hyperv/hyperv.c: In function ‘hyperv_hcall_signal_event’: hw/hyperv/hyperv.c:683:17: error: implicit declaration of function ‘ldq_phys’; did you mean ‘ldub_phys’? [-Werror=implicit-function-declaration] 683 | param = ldq_phys(&address_space_memory, addr); | ^~~~~~~~ | ldub_phys hw/hyperv/hyperv.c:683:17: error: nested extern declaration of ‘ldq_phys’ [-Werror=nested-externs] hw/hyperv/hyperv.c: In function ‘hyperv_hcall_retreive_dbg_data’: hw/hyperv/hyperv.c:792:24: error: ‘TARGET_PAGE_SIZE’ undeclared (first use in this function); did you mean ‘TARGET_PAGE_BITS’? 792 | msg.u.recv.count = TARGET_PAGE_SIZE - sizeof(*debug_data_out); | ^~~~~~~~~~~~~~~~ | TARGET_PAGE_BITS hw/hyperv/hyperv.c: In function ‘hyperv_syndbg_send’: hw/hyperv/hyperv.c:885:16: error: ‘HV_SYNDBG_STATUS_INVALID’ undeclared (first use in this function) 885 | return HV_SYNDBG_STATUS_INVALID; | ^~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | hw/intc/xics: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé2024-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include missing headers in order to avoid when refactoring unrelated headers: hw/intc/xics.c: In function 'icp_realize': hw/intc/xics.c:304:5: error: unknown type name 'PowerPCCPU' 304 | PowerPCCPU *cpu; | ^~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | hw/arm: Add `\n` to hint messageGreg Kurz2024-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | error_printf() doesn't add newlines. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | hw/loongarch: Add `\n` to hint messageGreg Kurz2024-01-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | error_printf() doesn't add newlines. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | hw/i386: Add `\n` to hint messageGreg Kurz2024-01-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | error_printf() doesn't add newlines. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | cxl: Clean up includesPeter Maydell2024-01-301-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit was created with scripts/clean-includes. All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | acpi: Clean up includesPeter Maydell2024-01-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit was created with scripts/clean-includes: ./scripts/clean-includes --git acpi include/hw/*/*acpi.h hw/*/*acpi.c All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | aspeed: Clean up includesPeter Maydell2024-01-302-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit was created with scripts/clean-includes. All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| * | hyperv: Clean up includesPeter Maydell2024-01-306-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit was created with scripts/clean-includes: ./scripts/clean-includes --git hyperv hw/hyperv/*.[ch] All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* | | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingPeter Maydell2024-01-315-15/+29
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull request # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmW5b1IACgkQnKSrs4Gr # c8geoQf8DU8Z8jlvy1luuBZLq3R7hnC7c3Wzje0atLGP++pX6QUXfAgGDsTTIQeh # XWmkFhbOBurhToH8YpgPyNG8ZWYd9+NIvLnIJiWDklNDZg2zC00aOi8yBEbsgyFb # 50HJA30AAHq8PuctCzhGhENLxvBvNDNME74SwYH7FSIK5x/nA1XBHDZsjst1/Hk2 # 1loLbVWElbU28Xll7hI862SAb8RULC/sRQomkQAhpydxq4TApNuRwvpRfPNFwFJ0 # +dCquCJEfV6wfD62xg2CBGA5DrD9T7ADxmCYl4DQyp3HIRKXAptjgLsx3aZaIr1z # KAnCRNUXRuLgRZf7b9I+HhxGISoNng== # =/bBL # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Jan 2024 21:51:14 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: hw/block/block.c: improve confusing blk_check_size_and_read_all() error hw/core/qdev.c: add qdev_get_human_name() pflash: fix sectors vs bytes confusion in blk_pread_nonzeroes() block/blkio: Make s->mem_region_alignment be 64 bits block/io_uring: improve error message when init fails Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | hw/block/block.c: improve confusing blk_check_size_and_read_all() errorManos Pitsidianakis2024-01-304-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In cases where a device tries to read more bytes than the block device contains, the error is vague: "device requires X bytes, block backend provides Y bytes". This patch changes the errors of this function to include the block backend name, the device id and device type name where appropriate. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-id: 7260eadff22c08457740117c1bb7bd2b4353acb9.1706598705.git.manos.pitsidianakis@linaro.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | hw/core/qdev.c: add qdev_get_human_name()Manos Pitsidianakis2024-01-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a simple method to return some kind of human readable identifier for use in error messages. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-id: 8b566bfced98ae44be1fcc1f8e7215f0c3393aa1.1706598705.git.manos.pitsidianakis@linaro.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | pflash: fix sectors vs bytes confusion in blk_pread_nonzeroes()Stefan Hajnoczi2024-01-301-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following expression is incorrect because blk_pread_nonzeroes() deals in units of bytes, not sectors: bytes = MIN(size - offset, BDRV_REQUEST_MAX_SECTORS) ^^^^^^^ BDRV_REQUEST_MAX_BYTES is the appropriate constant. Fixes: a4b15a8b9ef2 ("pflash: Only read non-zero parts of backend image") Cc: Xiang Zheng <zhengxiang9@huawei.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240130002712.257815-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* | Merge tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell2024-01-301-1/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | linux-user: Allow gdbstub to ignore page protection cpu-exec: simplify jump cache management include/exec: Cleanups toward building accel/tcg once # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW4LXcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+CgAf8CdqkvKsUK9/5bu99 # 9E4kRBkR8KqWYvBfRs4IFmjoEdEa4sCujWrHliOcW7Kh+XlVyAPI9rZG32QkxCEQ # hi9WXieXjfPLTTmrbeiq7cwxztSj8Z55wwvbxkrtFyGDQ0AMccp49tAvfejEb6VD # Ssx96nWQDgryLrn+My+wMQjl9aVKUWp5vB8k12aAcpRXPH2yoGE2JHAZ1C743nA6 # rShiJAT78HwERcMXDeYmmriYg0s4Z4+A6ErTiXDnFgj87YanHZc0I/55G5Sh+pW8 # REicD3jwS0GHOOHL0K781FopE1wTM442GLVxobXoxUXsHEiO+3TK5JdEIqvSstYA # fRB8Pg== # =xZOe # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Jan 2024 22:57:59 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240130' of https://gitlab.com/rth7680/qemu: (31 commits) target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler accel/tcg: Inline need_replay_interrupt target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c target/loongarch: Constify loongarch_tcg_ops include/qemu: Add TCGCPUOps typedef to typedefs.h accel/tcg: Un-inline icount_exit_request() for clarity accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson accel/tcg: Move perf and debuginfo support to tcg/ accel/tcg: Remove #ifdef TARGET_I386 from perf.c tcg: Make tb_cflags() usable from target-agnostic code accel/tcg: Make use of qemu_target_page_mask() in perf.c target: Make qemu_target_page_mask() available for *-user accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD tests/tcg: Add the PROT_NONE gdbstub test tests/tcg: Factor out gdbstub test functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * accel/tcg: Move perf and debuginfo support to tcg/Ilya Leoshkevich2024-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tcg/ should not depend on accel/tcg/, but perf and debuginfo support provided by the latter are being used by tcg/tcg.c. Since that's the only user, move both to tcg/. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231212003837.64090-5-iii@linux.ibm.com> Message-Id: <20240125054631.78867-5-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | vfio/pci: Clear MSI-X IRQ index alwaysCédric Le Goater2024-01-291-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing device assignment of a physical device, MSI-X can be enabled with no vectors enabled and this sets the IRQ index to VFIO_PCI_MSIX_IRQ_INDEX. However, when MSI-X is disabled, the IRQ index is left untouched if no vectors are in use. Then, when INTx is enabled, the IRQ index value is considered incompatible (set to MSI-X) and VFIO_DEVICE_SET_IRQS fails. QEMU complains with : qemu-system-x86_64: vfio 0000:08:00.0: Failed to set up TRIGGER eventfd signaling for interrupt INTX-0: VFIO_DEVICE_SET_IRQS failure: Invalid argument To avoid that, unconditionaly clear the IRQ index when MSI-X is disabled. Buglink: https://issues.redhat.com/browse/RHEL-21293 Fixes: 5ebffa4e87e7 ("vfio/pci: use an invalid fd to enable MSI-X") Cc: Jing Liu <jing2.liu@intel.com> Cc: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>