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* Merge tag 'pull-target-arm-20240202' of ↵Peter Maydell2024-02-0231-212/+1518
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Connect SPI Controller to BCM2835Rayhan Faizel2024-02-022-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will allow the SPI controller to be accessible from BCM2835 based boards as SPI0. SPI driver is usually disabled by default and config.txt does not work. Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-3-rayhan.faizel@gmail.com [PMM: indent tweak] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/ssi: Implement BCM2835 SPI ControllerRayhan Faizel2024-02-023-0/+293
| | | | | | | | | | | | | | | | | | | | This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/net: GMAC Tx ImplementationNabih Estefan Diaz2024-02-022-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implementation of Transmit function for packets - Implementation for reading and writing from and to descriptors in memory for Tx Added relevant trace-events NOTE: This function implements the steps detailed in the datasheet for transmitting messages from the GMAC. Change-Id: Icf14f9fcc6cc7808a41acd872bca67c9832087e6 Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-6-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/net: GMAC Rx ImplementationNabih Estefan Diaz2024-02-022-2/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Implementation of Receive function for packets - Implementation for reading and writing from and to descriptors in memory for Rx When RX starts, we need to flush the queued packets so that they can be received by the GMAC device. Without this it won't work with TAP NIC device. When RX descriptor list is full, it returns a DMA_STATUS for software to handle it. But there's no way to indicate the software has handled all RX descriptors and the whole pipeline stalls. We do something similar to NPCM7XX EMC to handle this case. 1. Return packet size when RX descriptor is full, effectively dropping these packets in such a case. 2. When software clears RX descriptor full bit, continue receiving further packets by flushing QEMU packet queue. Added relevant trace-events Change-Id: I132aa254a94cda1a586aba2ea33bbfc74ecdb831 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-5-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm: Add GMAC devices to NPCM7XX SoCHao Wu2024-02-021-2/+35
| | | | | | | | | | | | | | | | | | | | Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-3-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/net: Add NPCMXXX GMAC deviceHao Wu2024-02-023-1/+480
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the basic registers of GMAC device and sets registers for networking functionalities. Squashed IRQ Implementation patch into this one for compliation. Tested: The following message shows up with the change: Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (mii_bus:phy_addr=stmmac-0:00, irq=POLL) stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx Change-Id: If71c6d486b95edcccba109ba454870714d7e0940 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-2-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/xen: convert stderr prints to error/warn reportsManos Pitsidianakis2024-02-022-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the QEMU Coding Style document: > Do not use printf(), fprintf() or monitor_printf(). Instead, use > error_report() or error_vreport() from error-report.h. This ensures the > error is reported in the right place (current monitor or stderr), and in > a uniform format. > Use error_printf() & friends to print additional information. This commit changes fprintfs that report warnings and errors to the appropriate report functions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 42a8953553cf68e8bacada966f93af4fbce45919.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/xen/xen-hvm-common.c: convert DPRINTF to tracepointsManos Pitsidianakis2024-02-022-18/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tracing DPRINTFs to stderr might not be desired. A developer that relies on tracepoints should be able to opt-in to each tracepoint and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into tracepoints. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: b000ab73022dfeb7a7ab0ee8fd0f41fb208adaf0.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/xen/xen-mapcache.c: convert DPRINTF to tracepointsManos Pitsidianakis2024-02-022-30/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tracing DPRINTFs to stderr might not be desired. A developer that relies on tracepoints should be able to opt-in to each tracepoint and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into tracepoints. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 2fbe1fbc59078e384761c932e97cfa4276a53d75.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reportsManos Pitsidianakis2024-02-022-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tracing DPRINTFs to stderr might not be desired. A developer that relies on trace events should be able to opt-in to each trace event and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into trace events. Errors or warnings are converted to error_report and warn_report calls. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: fe5e3bd54231abe933f95a24e0e88208cd8cfd8f.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/z2: convert DPRINTF to trace events and guest errorsManos Pitsidianakis2024-02-022-19/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tracing DPRINTFs to stderr might not be desired. A developer that relies on trace events should be able to opt-in to each trace event and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into trace events. DPRINTFs that report guest errors are logged with LOG_GUEST_ERROR. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 799c5141c5751cf2341e1d095349612e046424a8.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/strongarm.c: convert DPRINTF to trace events and guest errorsManos Pitsidianakis2024-02-022-30/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tracing DPRINTFs to stderr might not be desired. A developer that relies on trace events should be able to opt-in to each trace event and rely on QEMU's log redirection, instead of stderr by default. This commit converts DPRINTFs in this file that are used for tracing into trace events. DPRINTFs that report guest errors are logged with LOG_GUEST_ERROR.# Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 39db71dd87bf2007cf7812f3d91dde53887f1f2f.1706544115.git.manos.pitsidianakis@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * pci-host: designware: Limit value range of iATU viewport registerGuenter Roeck2024-02-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest version of qemu (v8.2.0-869-g7a1dc45af5) crashes when booting the mcimx7d-sabre emulation with Linux v5.11 and later. qemu-system-arm: ../system/memory.c:2750: memory_region_set_alias_offset: Assertion `mr->alias' failed. Problem is that the Designware PCIe emulation accepts the full value range for the iATU Viewport Register. However, both hardware and emulation only support four inbound and four outbound viewports. The Linux kernel determines the number of supported viewports by writing 0xff into the viewport register and reading the value back. The expected value when reading the register is the highest supported viewport index. Match that code by masking the supported viewport value range when the register is written. With this change, the Linux kernel reports imx6q-pcie 33800000.pcie: iATU: unroll F, 4 ob, 4 ib, align 0K, limit 4G as expected and supported. Fixes: d64e5eabc4c7 ("pci: Add support for Designware IP block") Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Nikita Ostrenkov <n.ostrenkov@gmail.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20240129060055.2616989-1-linux@roeck-us.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/zynq: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé2024-02-021-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/vexpress: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé2024-02-021-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[]Philippe Mathieu-Daudé2024-02-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npcm7xx Soc is created with a Cortex-A9 core, see in hw/arm/npcm7xx.c: static void npcm7xx_init(Object *obj) { NPCM7xxState *s = NPCM7XX(obj); for (int i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { object_initialize_child(obj, "cpu[*]", &s->cpu[i], ARM_CPU_TYPE_NAME("cortex-a9")); } The MachineClass::default_cpu_type field is ignored: delete it. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[]Philippe Mathieu-Daudé2024-02-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Musca boards use the embedded subsystems (SSE) tied to a specific Cortex core. Our models only use the Cortex-M33. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]Philippe Mathieu-Daudé2024-02-022-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/highbank: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé2024-02-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restrict MachineClass::valid_cpu_types[] to the single valid CPU types. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (midway-machine) /cpu[0] (cortex-a15-arm-cpu) ... we now display an error: $ qemu-system-arm -M midway -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a15 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240129151828.59544-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/highbank: Add missing QOM parent for CPU coresPhilippe Mathieu-Daudé2024-02-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240129151828.59544-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/exynos: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé2024-02-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (nuri-machine) /soc (exynos4210) /cpu[0] (cortex-a9-arm-cpu) ... We now display an error: $ qemu-system-arm -M nuri -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a9 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240129151828.59544-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/arm/exynos: Add missing QOM parent for CPU coresPhilippe Mathieu-Daudé2024-02-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20240129151828.59544-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * hw/core: Remove transitional infrastructure from BusClassPeter Maydell2024-02-021-67/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BusClass currently has transitional infrastructure to support subclasses which implement the legacy BusClass::reset method rather than the Resettable interface. We have now removed all the users of BusClass::reset in the tree, so we can remove the transitional infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-6-peter.maydell@linaro.org
| * hw/s390x/css-bridge: switch virtual-css bus to 3-phase-resetPeter Maydell2024-02-021-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the s390x virtual-css bus from using BusClass::reset to the Resettable interface. This has no behavioural change, because the BusClass code to support subclasses that use the legacy BusClass::reset will call that method in the hold phase of 3-phase reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-5-peter.maydell@linaro.org
| * adb: Switch bus reset to 3-phase-resetPeter Maydell2024-02-021-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the ADB bus from using BusClass::reset to the Resettable interface. This has no behavioural change, because the BusClass code to support subclasses that use the legacy BusClass::reset will call that method in the hold phase of 3-phase reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-4-peter.maydell@linaro.org
| * vmbus: Switch bus reset to 3-phase-resetPeter Maydell2024-02-021-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch vmbus from using BusClass::reset to the Resettable interface. This has no behavioural change, because the BusClass code to support subclasses that use the legacy BusClass::reset will call that method in the hold phase of 3-phase reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-3-peter.maydell@linaro.org
| * pci: Switch bus reset to 3-phase-resetPeter Maydell2024-02-021-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the PCI bus from using BusClass::reset to the Resettable interface. This has no behavioural change, because the BusClass code to support subclasses that use the legacy BusClass::reset will call that method in the hold phase of 3-phase reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-2-peter.maydell@linaro.org
* | hw/pci: remove pci_nic_init_nofail()David Woodhouse2024-02-021-72/+0
| | | | | | | | | | | | | | | | This function is no longer used, as all its callers have been converted to use pci_init_nic_devices() instead. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/xtensa/xtfpga: use qemu_create_nic_device()David Woodhouse2024-02-021-7/+6
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/sparc/sun4m: use qemu_find_nic_info()David Woodhouse2024-02-021-6/+14
| | | | | | | | | | | | | | | | Obtain the MAC address from the NIC configuration if there is one, or generate one explicitly so that it can be placed in the PROM. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/s390x/s390-virtio-ccw: use qemu_create_nic_device()David Woodhouse2024-02-021-9/+2
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Acked-by: Thomas Huth <thuth@redhat.com>
* | hw/riscv: use qemu_configure_nic_device()David Woodhouse2024-02-022-18/+3
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/openrisc/openrisc_sim: use qemu_create_nic_device()David Woodhouse2024-02-021-9/+9
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/net/lasi_i82596: use qemu_create_nic_device()David Woodhouse2024-02-022-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create the device only if there is a corresponding NIC config for it. Remove the explicit check on nd_table[0].used from hw/hppa/machine.c which (since commit d8a3220005d7) tries to do the same thing. The lasi_82596 support has been disabled since it was first introduced, since enable_lasi_lan() has always been zero. This allows the user to enable it by explicitly requesting a NIC model 'lasi_82596' or just using the alias 'lasi'. Otherwise, it defaults to a PCI NIC as before. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/net/lasi_i82596: Re-enable buildDavid Woodhouse2024-02-022-1/+2
| | | | | | | | | | | | | | | | | | | | | | When converting to the shiny build-system-du-jour, a typo prevented the last_i82596 driver from being built. Correct the config option name to re-enable the build. And include "sysemu/sysemu.h" so it actually builds. Fixes: b1419fa66558 ("meson: convert hw/net") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2144 Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/mips/jazz: use qemu_find_nic_info()David Woodhouse2024-02-021-8/+7
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/mips/mipssim: use qemu_create_nic_device()David Woodhouse2024-02-021-6/+7
| | | | | | | | | | | | | | | | | | The MIPS SIM platform instantiates its NIC only if a corresponding configuration exists for it. Use qemu_create_nic_device() function for that. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/microblaze: use qemu_configure_nic_device()David Woodhouse2024-02-022-4/+2
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/m68k/q800: use qemu_find_nic_info()David Woodhouse2024-02-021-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | If a corresponding NIC configuration was found, it will have a MAC address already assigned, so use that. Else, generate and assign a default one. Using qemu_find_nic_info() is simpler than the alternative of using qemu_configure_nic_device() and then having to fetch the "mac" property as a string and convert it. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/m68k/mcf5208: use qemu_create_nic_device()David Woodhouse2024-02-021-13/+6
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/net/etraxfs-eth: use qemu_configure_nic_device()David Woodhouse2024-02-022-8/+6
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm: use qemu_configure_nic_device()David Woodhouse2024-02-026-33/+10
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/stellaris: use qemu_find_nic_info()David Woodhouse2024-02-021-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Rather than just using qemu_configure_nic_device(), populate the MAC address in the system-registers device by peeking at the NICInfo before it's assigned to the device. Generate the MAC address early, if there is no matching -nic option. Otherwise the MAC address wouldn't be generated until net_client_init1() runs. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliasesDavid Woodhouse2024-02-021-7/+9
| | | | | | | | | | | | | | | | Also update the test to specify which device to attach the test socket to, and remove the comment lamenting the fact that we can't do so. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/highbank: use qemu_create_nic_device()David Woodhouse2024-02-021-7/+5
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/net/lan9118: use qemu_configure_nic_device()David Woodhouse2024-02-025-12/+9
| | | | | | | | | | | | | | | | | | Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preseve the existing behaviour for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/net/smc91c111: use qemu_configure_nic_device()David Woodhouse2024-02-026-37/+22
| | | | | | | | | | | | | | | | | | Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preserve the existing behaviour of each caller for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/fsl: use qemu_configure_nic_device()David Woodhouse2024-02-024-4/+4
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
* | hw/arm/exynos4: use qemu_create_nic_device()David Woodhouse2024-02-021-4/+2
| | | | | | | | | | Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>