summary refs log tree commit diff stats
path: root/hw (follow)
Commit message (Collapse)AuthorAgeFilesLines
...
| * ppc/xive2: redistribute irqs for pool and phys ctx pullGlenn Miles2025-07-212-33/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When disabling (pulling) an xive interrupt context, we need to redistribute any active group interrupts to other threads that can handle the interrupt if possible. This support had already been added for the OS context but had not yet been added to the pool or physical context. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-28-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Redistribute group interrupt precluded by CPPR updateGlenn Miles2025-07-211-22/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for redistributing a presented group interrupt if it is precluded as a result of changing the CPPR value. Without this, group interrupts can be lost. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-27-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA opGlenn Miles2025-07-212-3/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting AIX in a PowerVM partition requires the use of the "Acknowledge O/S Interrupt to even O/S reporting line" special operation provided by the IBM XIVE interrupt controller. This operation is invoked by writing a byte (data is irrelevant) to offset 0xC10 of the Thread Interrupt Management Area (TIMA). It can be used by software to notify the XIVE logic that the interrupt was received. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-26-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Improve pool regs variable nameGlenn Miles2025-07-211-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Change pregs to pool_regs, for clarity. [npiggin: split from larger patch] Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-25-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Add more interrupt notification tracingGlenn Miles2025-07-213-5/+17
| | | | | | | | | | | | | | | | | | | | | | Add more tracing around notification, redistribution, and escalation. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-24-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Support redistribution of group interruptsGlenn Miles2025-07-211-4/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an XIVE context is pulled while it has an active, unacknowledged group interrupt, XIVE will check to see if a context on another thread can handle the interrupt and, if so, notify that context. If there are no contexts that can handle the interrupt, then the interrupt is added to a backlog and XIVE will attempt to escalate the interrupt, if configured to do so, allowing the higher privileged handler to activate a context that can handle the original interrupt. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-23-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: add interrupt priority configuration flagsGlenn Miles2025-07-212-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for extracting additional configuration flags from the XIVE configuration register that are needed for redistribution of group interrupts. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-22-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * pnv/xive2: Permit valid writes to VC/PC Flush Control registersMichael Kowal2025-07-211-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writes to the Flush Control registers were logged as invalid when they are allowed. Clearing the unsupported want_cache_disable feature is supported, so don't log an error in that case. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-21-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULLNicholas Piggin2025-07-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC register, so don't clear it on read. Don't bother clearing the reads-as-zero CONFLICT bit because it's masked at write already. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-20-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * pnv/xive2: Print value in invalid register write loggingMichael Kowal2025-07-211-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This can make it easier to see what the target system is trying to do. [npiggin: split from larger patch] Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-19-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * pnv/xive2: Support ESB EscalationGlenn Miles2025-07-211-12/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for XIVE ESB Interrupt Escalation. Suggested-by: Michael Kowal <kowal@linux.ibm.com> [This change was taken from a patch provided by Michael Kowal.] Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-18-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Fix pulling pool and phys contextsNicholas Piggin2025-07-211-8/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This improves the implementation of pulling pool and phys contexts in XIVE1, by following closer the OS pulling code. In particular, the old ring data is returned rather than the modified, and irq signals are reset on pull. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-17-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Move NSR decoding into helper functionsNicholas Piggin2025-07-211-9/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than functions to return masks to test NSR bits, have functions to test those bits directly. This should be no functional change, it just makes the code more readable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-16-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Explicitly zero NSR after acceptingNicholas Piggin2025-07-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Have xive_tctx_accept clear NSR in one shot rather than masking out bits as they are tested, which makes it clear it's reset to 0, and does not have a partial NSR value in the register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-15-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: tctx_notify should clear the precluded interruptNicholas Piggin2025-07-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If CPPR is lowered to preclude the pending interrupt, NSR should be cleared and the qemu_irq should be lowered. This avoids some cases of supurious interrupts. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-14-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Set CPPR delivery should account for group priorityNicholas Piggin2025-07-211-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The group interrupt delivery flow selects the group backlog scan if LSMFB < IPB, but that scan may find an interrupt with a priority >= IPB. In that case, the VP-direct interrupt should be chosen. This extends to selecting the lowest prio between POOL and PHYS rings. Implement this just by re-starting the selection logic if the backlog irq was not found or priority did not match LSMFB (LSMFB is updated so next time around it would see the right value and not loop infinitely). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-13-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPRNicholas Piggin2025-07-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Group interrupts should not be taken from the backlog and presented if they are precluded by CPPR. Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS context") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-12-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Fix treatment of PIPR in CPPR updateGlenn Miles2025-07-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the XIVE spec, updating the CPPR should also update the PIPR. The final value of the PIPR depends on other factors, but it should never be set to a value that is above the CPPR. Also added support for redistributing an active group interrupt when it is precluded as a result of changing the CPPR value. Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-11-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Fix irq preempted by lower priority group irqGlenn Miles2025-07-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A problem was seen where uart interrupts would be lost resulting in the console hanging. Traces showed that a lower priority interrupt was preempting a higher priority interrupt, which would result in the higher priority interrupt never being handled. The new interrupt's priority was being compared against the CPPR (Current Processor Priority Register) instead of the PIPR (Post Interrupt Priority Register), as was required by the XIVE spec. This allowed for a window between raising an interrupt and ACK'ing the interrupt where a lower priority interrupt could slip in. Fixes: 26c55b99418 ("ppc/xive2: Process group backlog when updating the CPPR") Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-10-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Use fair irq target search algorithmGlenn Miles2025-07-211-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current xive algorithm for finding a matching group vCPU target always uses the first vCPU found. And, since it always starts the search with thread 0 of a core, thread 0 is almost always used to handle group interrupts. This can lead to additional interrupt latency and poor performance for interrupt intensive work loads. Changing this to use a simple round-robin algorithm for deciding which thread number to use when starting a search, which leads to a more distributed use of threads for handling group interrupts. [npiggin: Also round-robin among threads, not just cores] Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-9-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Reset Generation Flipped bit on END Cache WatchMichael Kowal2025-07-212-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the END Event Queue wraps the END EQ Generation bit is flipped and the Generation Flipped bit is set to one. On a END cache Watch read operation, the Generation Flipped bit needs to be reset. While debugging an error modified END not valid error messages to include the method since all were the same. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-8-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Fix PHYS NSR ring matchingNicholas Piggin2025-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Test that the NSR exception bit field is equal to the pool ring value, rather than any common bits set, which is more correct (although there is no practical bug because the LSI NSR type is not implemented and POOL/PHYS NSR are encoded with exclusive bits). Fixes: 4c3ccac636 ("pnv/xive: Add special handling for pool targets") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-7-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: fix context push calculation of IPB priorityNicholas Piggin2025-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Pushing a context and loading IPB from NVP is defined to merge ('or') that IPB into the TIMA IPB register. PIPR should therefore be calculated based on the final IPB value, not just the NVP value. Fixes: 9d2b6058c5b ("ppc/xive2: Add grouping level to notification") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-6-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Remote VSDs need to match on forwarding addressMichael Kowal2025-07-211-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a multi chip environment there will be remote/forwarded VSDs. The check to find a matching INT controller (XIVE) of the remote block number was checking the INTs chip number. Block numbers are not tied to a chip number. The matching remote INT is the one that matches the forwarded VSD address with VSD types associated MMIO BAR. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-5-npiggin@gmail.com [ clg: Fixed log format in pnv_xive2_get_remote() ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive2: Fix calculation of END queue sizesGlenn Miles2025-07-211-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The queue size of an Event Notification Descriptor (END) is determined by the 'cl' and QsZ fields of the END. If the cl field is 1, then the queue size (in bytes) will be the size of a cache line 128B * 2^QsZ and QsZ is limited to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited to 12. Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-4-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Report access size in XIVE TM operation error logsNicholas Piggin2025-07-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Report access size in XIVE TM operation error logs. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-3-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * ppc/xive: Fix xive trace event outputNicholas Piggin2025-07-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Typo, IBP should be IPB. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Reviewed-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com> Tested-by: Gautam Menghani <gautam@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-2-npiggin@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
* | Merge tag 'display-20250718-pull-request' of https://gitlab.com/kraxel/qemu ↵Stefan Hajnoczi2025-07-2111-15/+54
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Load ramfb vgabios on x86 only. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmh6o80ACgkQTLbY7tPo # cTjxPBAAktTXxFK6loSMSWC1ul8RCl/4F7G84J4eT+Ui8/KIG8do5KcebTnXb9zo # keOG7n9HPk4fROWiAFgGnuBfw41DWmLDS34iuENrG3X26TQgSSgBveuwas67Pzqu # HpaFSxjh7BRLlkUWaNoll57cDM3kKLmx+Onw6m/7kbcVXAsy1N4wxfCT1faUU7ID # R1ggULG1WhB8q+YtQjac6EfOpdHe1BTBGLuxSwE3mNkce9ZP7C8uxZTCR5PXggZi # IXzJzGpFRDCHqrilWksiE62yF20Kem4ZcpO/GgLWmF+X+DYBDEWcajihvF20TGUL # n6dyT7MBxuvqFy0OtBPHNcnq2PZzOIKyxyMvBg9402xeD6goNbFKloAYeae4C9u0 # QuqQUpb8D3lVagVu55N5XfpdMHR0P8yefPAjaFL4o3rf2JSjyI6MRX/+2eA7aXcX # xiwHSx3iavEeNQNsPZsS3JhH5bKy/zkWRiBd+msGVAYMZGzhdEtLg/w8yUd6dQ5p # /3Y3F4fL6T6QSwhsiihcbdPtjhfVCP09MYK/P4cIFbWOzjfbndt1/UIXHQ54s8Jo # PShcE7QH7ttT2gK5nFPG5yeTqF70kKpSyhwF2pukf2fAgcU+0SNoj2zZNtHAvKeh # 8EHqAy8m1J4AlQeO5nT9tJj/v1CM0q6cljzIfV8hWWgM/hL/vLc= # =76m5 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 18 Jul 2025 15:43:09 EDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'display-20250718-pull-request' of https://gitlab.com/kraxel/qemu: hw/i386: Add the ramfb romfile compatibility vfio: Move the TYPE_* to hw/vfio/types.h ramfb: Add property to control if load the romfile Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Conflicts: hw/core/machine.c Context conflict because the vfio-pci "x-migration-load-config-after-iter" was added recently.
| * | hw/i386: Add the ramfb romfile compatibilityShaoqin Huang2025-07-186-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ramfb is a sysbus device so it can only used for machine types where it is explicitly enabled: # git grep machine_class_allow_dynamic_sysbus_dev.*TYPE_RAMFB_DEVICE hw/arm/virt.c: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); hw/i386/microvm.c: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); hw/i386/pc_piix.c: machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); hw/i386/pc_q35.c: machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE); hw/loongarch/virt.c: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); hw/riscv/virt.c: machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); So these six are the only machine types we have to worry about. The three x86 machine types (pc, q35, microvm) will actually use the rom (when booting with seabios). For arm/riscv/loongarch virt we want to disable the rom. This patch sets ramfb romfile option to false by default, except for x86 machines types (pc, q35, microvm) which need the rom file when booting with seabios and machine types <= 10.0 (handling the case of arm virt, for compat reasons). At the same time, set the "use-legacy-x86-rom" property to true on those historical versioned machine types in order to avoid the memory layout being changed. Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Message-ID: <20250717100941.2230408-4-shahuang@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | vfio: Move the TYPE_* to hw/vfio/types.hShaoqin Huang2025-07-182-9/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the TYPE_* to a new file hw/vfio/types.h because the TYPE_VFIO_PCI will be used in later patch, but directly include the hw/vfio/pci.h can cause some compilation error when cross build the windows version. The hw/vfio/types.h can be included to mitigate that problem. Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Message-ID: <20250717100941.2230408-3-shahuang@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
| * | ramfb: Add property to control if load the romfileShaoqin Huang2025-07-176-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the ramfb device loads the vgabios-ramfb.bin unconditionally, but only the x86 need the vgabios-ramfb.bin, this can cause that when use the release package on arm64 it can't find the vgabios-ramfb.bin. Because only seabios will use the vgabios-ramfb.bin, load the rom logic is x86-specific. For other !x86 platforms, the edk2 ships an EFI driver for ramfb, so they don't need to load the romfile. So add a new property use-legacy-x86-rom in both ramfb and vfio_pci device, because the vfio display also use the ramfb_setup() to load the vgabios-ramfb.bin file. After have this property, the machine type can set the compatibility to not load the vgabios-ramfb.bin if the arch doesn't need it. For now the default value is true but it will be turned off by default in subsequent patch when compats get properly handled. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shaoqin Huang <shahuang@redhat.com> Message-ID: <20250717100941.2230408-2-shahuang@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* | | Merge tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi2025-07-212-1/+14
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging target-arm queue: * hvf: arm: Remove $pc from trace_hvf_data_abort() * target/arm: Correct encoding of Debug Communications Channel registers * hw/misc/ivshmem-pci: Improve error handling * target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode * host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() * hw/misc/max78000_aes: Comment Internal Key Storage * docs: Fix Aspeed title * Implement a handful of missing FEAT_SVE_B16_B16 insns * Fix bugs in FMAXQV, FMINQV, etc * Fix assert in LD1Q decode * hvf: arm: Add permission check in GIC sysreg handlers * hvf: arm: Emulate ICC_RPR_EL1 accesses properly * accel/hvf: Display executable bit as 'X' # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmh+OlgZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3klRD/0QvWyi0z0wbBdIKGi8kury # VP/S1FcqP2w9l0jUAmINxsOYu/+ql8w3t6m2jxlTOYZc9rNauQrxRYGD1GdqfJVn # VCYN47OHRye+iMH6c5jdKyJTi3n2uvT2g8anh2Yt18xOey45Pwr2fTs8rje3N5sH # fvv1mNaeGyA7wgXEY9Z4tEvW19ZPsuKIBd4Ea7klDXwUpTmmQkJMVTKyz7/TefqK # YicpM9E4dMxwNvW/8zrsVH505E4s15OytIjhDci30v2M7Uh3tUIRKo+s44Kk7cEq # HIwO/ra1HEhp8xGU2UfRf643EF1k7A0VUgetHSxYbi1gIknjiSU8Ohnd268CgY7G # /UbjgjFu5mcJgBvoNCwGy0iuCkEfRZ+veq24OjL6GbMvt2utCm9Rumu5KLemLpvW # mB4RexjbT+FDldhz8Ub42sR96UpZ0TSEfwjOswHibA4Zk4o2S6fRv0OqaBMB2dKU # MhcMdBdPXe3SmecRlYoqde+RCUyIOMD46uiJYrBhG6Nfn6SgcnS+ZGB960veaH2r # p5lvyJIBn3/a1KwOET9z5Gp3C6l4TXgJjIaCB4qAWHxeBR/AIobRC71heCc0uPU+ # J3Nm5/p6rcz0vjzs1To0VuXM57qNpQJWu0Un+8CDjpXJ0piyBk4o2iu1dw26bsMs # yrgqlMfDsXNlK/yUdykAbw== # =rQ+N # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 09:02:16 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu: accel/hvf: Display executable bit as 'X' hvf: arm: Emulate ICC_RPR_EL1 accesses properly hvf: arm: Add permission check in GIC sysreg handlers target/arm: Make LD1Q decode and trans fn agree about a->u target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV target/arm: Don't nest H() macro calls in SVE DO_REDUCE target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV target/arm: Add BFMLA, BFMLS (indexed) target/arm: Add BFMLA, BFMLS (vectors) target/arm: Add BFMUL (indexed) target/arm: Add BFMIN, BFMAX (predicated) target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated) target/arm: Add BFADD, BFSUB, BFMUL (unpredicated) docs: Fix Aspeed title hw/misc/max78000_aes: Comment Internal Key Storage host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode hw/misc/ivshmem-pci: Improve error handling target/arm: Correct encoding of Debug Communications Channel registers hvf: arm: Remove $pc from trace_hvf_data_abort() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | hw/misc/max78000_aes: Comment Internal Key StorageJackson Donaldson2025-07-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity Scan noted an unusual pattern in the MAX78000 aes device, with duplicated calls to set_decrypt. This commit adds a comment noting why the implementation is correct. Signed-off-by: Jackson Donaldson <jcksn@duck.com> Message-id: 20250716002622.84685-1-jcksn@duck.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | | hw/misc/ivshmem-pci: Improve error handlingPeter Maydell2025-07-211-1/+8
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity points out that the ivshmem-pci code has some error handling cases where it incorrectly tries to use an invalid filedescriptor. These generally happen because ivshmem_recv_msg() calls qemu_chr_fe_get_msgfd(), which might return -1, but the code in process_msg() generally assumes that the file descriptor was provided when it was supposed to be. In particular: * the error case in process_msg() only needs to close the fd if one was provided * process_msg_shmem() should fail if no fd was provided Coverity: CID 1508726 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 20250711145012.1521936-1-peter.maydell@linaro.org
* | | hw/net/npcm_gmac.c: Drop 'buf' local variablePeter Maydell2025-07-211-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the local variable 'buf' only when we call dma_memory_read(), and it is always set to &tx_send_buffer[prev_buf_size] immediately before both of those calls. So remove the variable and pass tx_send_buffer + prev_buf_size to dma_memory_read(). This fixes in passing a place where we set buf = tx_send_buffer but never used that value because we always updated buf to something else later before using it. Coverity: CID 1534027 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | | hw/net/npcm_gmac.c: Correct test for when to reallocate packet bufferPeter Maydell2025-07-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gmac_try_send_next_packet() we have code that does "if this block of data won't fit in the buffer, reallocate it". However, the condition it uses is if ((prev_buf_size + tx_buf_len) > sizeof(buf)) where buf is a uint8_t *. This means that sizeof(buf) is always 8 bytes, and the condition will almost always be true, so we will reallocate the buffer more often than we need to. Correct the condition to test against tx_buffer_size, which is where we track how big the allocated buffer is. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | | hw/net/npcm_gmac.c: Unify length and prev_buf_size variablesPeter Maydell2025-07-211-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the bug fix in the previous commit, the length and prev_buf_size variables are identical, except that prev_buf_size is uint32_t and length is uint16_t. We can therefore unify them. The only place where the type makes a difference is that we will truncate the packet at 64K when sending it; this commit preserves that behaviour by using a local variable when doing the packet send. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | | hw/net/npcm_gmac.c: Send the right data for second packet in a rowPeter Maydell2025-07-211-0/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The transmit loop in gmac_try_send_next_packet() is constructed in a way that means it will send incorrect data if it it sends more than one packet. The function assembles the outbound data in a dynamically allocated block of memory which is pointed to by tx_send_buffer. We track the first point in this block of memory which is not yet used with the prev_buf_size offset, initially zero. We track the size of the packet we're sending with the length variable, also initially zero. As we read chunks of data out of guest memory, we write them to tx_send_buffer[prev_buf_size], and then increment both prev_buf_size and length. (We might dynamically reallocate the buffer if needed.) When we send a packet, we checksum and send length bytes, starting at tx_send_buffer, and then we reset length to 0. This gives the right data for the first packet. But we don't reset prev_buf_size. This means that if we process more descriptors with further data for the next packet, that data will continue to accumulate at offset prev_buf_size, i.e. after the data for the first packet. But when we transmit that second packet, we send length bytes from tx_send_buffer, so we will send a packet which has the length of the second packet but the data of the first one. The fix for this is to also clear prev_buf_size after the packet has been sent -- we never need the data from packet one after we've sent it, so we can write packet two's data starting at the beginning of the buffer. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
* | Merge tag 'pull-9p-20250716' of https://github.com/cschoenebeck/qemu into ↵Stefan Hajnoczi2025-07-172-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging 9pfs changes: * Tightens printf-style format checks. No behaviour change. # -----BEGIN PGP SIGNATURE----- # # iQJLBAABCgA1FiEEltjREM96+AhPiFkBNMK1h2Wkc5UFAmh3npwXHHFlbXVfb3Nz # QGNydWRlYnl0ZS5jb20ACgkQNMK1h2Wkc5Wx4Q//QRpsmNSyIJmIrccvglFg5Okv # dTRMQYIaYgj45MgCp+/+JSwkDtKkC7oshe4FHabLgKq7mapuEpUcWu2JGa8SuY7O # Zm5VfGnxIo3Cwlm3pNBfVxQbr9DnbMgCJmspKRGv0gvkXAVtmDycILu27Okr333D # 4ftFLkXbOFRfoVj2ZAEMYYf7DwY0LDP5svA0ko6JgiyQbINKaA34FWq7LqT/XQd/ # K+SqPwtOG6OQY787omz/5IDhT0MwicWknsqrBzJTMER8qmu2T4A/7e7t7v+HRJBW # QGVIFPi4RFESQvzorSDDFTi7VgHaya47NeeyozkavrQKmkEGOXIZIItDLLQDf8FE # c/xMBUJijcmRNHctIVtk5H0H4YuC3twOmME+xoqm/bXWqpsg1kQWGrI5KQhfavtf # dVNj5FYpwK+kTAlUhAphcSLiZaQOLvoW8EfStD6I8PMvygP44SXTbpPrvSJzCzqx # /dtv6AQpuNrWKi1P14lJykXWJFTqlLPO7I0VJn+YK2R2lr2NE7qET7s7m+iqVFr/ # 3D+H15cMv8wPV+wkEbXSj4yZ96etY9D91Zv7i4c11jozMXR669tX3ObBOzM5rAOr # VFwGyCoc8MrSZ2Ah6N8WGNyYYkn98UbODpR1nGUIJVj8BPju5/eeqlFsOaD6PJIk # cx91MAoq/LyKcUytsX8= # =gNEm # -----END PGP SIGNATURE----- # gpg: Signature made Wed 16 Jul 2025 08:44:12 EDT # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * tag 'pull-9p-20250716' of https://github.com/cschoenebeck/qemu: hw/9pfs: move G_GNUC_PRINTF to header fsdev/9p-marshal: move G_GNUC_PRINTF to header Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | hw/9pfs: move G_GNUC_PRINTF to headerSean Wei2025-07-162-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v9fs_path_sprintf() is annotated with G_GNUC_PRINTF(2, 3) in hw/9pfs/9p.c, but the prototype in hw/9pfs/9p.h is missing the attribute, so callers that include only the header do not get format checking. Move the annotation to the header and delete the duplicate in the source file. No behavior change. Signed-off-by: Sean Wei <me@sean.taipei> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250613.qemu.9p.02@sean.taipei> [CS: fix code style (max. 80 chars per line)] Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
* | Merge tag 'accel-20250715' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-07-163-2/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accelerators patches - Unify x86/arm hw/xen/arch_hvm.h header - Move non-system-specific 'accel/accel-ops.h' and 'accel-cpu-ops.h' to accel/ - Move KVM definitions qapi/accelerator.json - Add @qom-type field to CpuInfoFast QAPI structure - Display CPU model name in 'info cpus' HMP command - Introduce @x-accel-stats QMP command - Add 'info accel' on HMP - Improve qemu_add_vm_change_state_handler*() docstring - Extract TCG statistic related code to tcg-stats.c - Implement AccelClass::get_[vcpu]_stats() handlers for TCG and HVF - Do not dump NaN in TCG statistics - Revert incomplete "accel/tcg: Unregister the RCU before exiting RR thread" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmh2r4UACgkQ4+MsLN6t # wN5i6xAAkOvwFh1GmsPUdz5RxzsWoIUDvyENg6E8Axwe5tSEMRFiPjabbTQJomQg # GZt75XIS24LZFZ+hvqrLSA+dFgXTgWv08ZE81EjwjmAMBlLCOPhCgeN6C1p8100Y # scSvRJbP9k9lpA5K7et/1X4AkK2cZyh+LGJgCjr2Al2mbERpPueDF8fxqeohFvXQ # nTSks4XlA0yQ06+9r49aQAiuXvgg9lDT1wIglD2HEV7vOVs/ud+yyL8+z5YMeFzx # pSIc6wDu4PqdA46w4MZs90uTy7S/PMvBiYDEiV3tKzg0MLttvFGlT58/YjVtguTP # mNkfwIEwQtDQzoxsFIJO7yBTlTRBs95V4aIVk3pB+Gb/bideRPIkeVQvgMSEBKj7 # N0pEXWOxfB9iIWO6b1utYpQ4uxeDOU/8DPUCit1IBbNgKTaJkJb77fboYk7NaB0K # KEtObAk6jMatB/xr+vUFWc4sMk9wlm72w8wcQzgKZ0xV2U3d1/Y/9nS4GvI510ev # TRQ3mKj7N319uCeId1czF6W8rillCJ2u8ZK53u+Nfp7R3PbsRSMc6IDJ1UdDUlyR # HFcWHxbcbEGhe8SnFGab4Qd6fWChcn2EaEoAJJz+Rqv0k3zcwqccNM5waCABAjTE # 0S22JIHePJKcpkMLGq3EOUAQuu+8Zsol7gPCLxSAMclVqPTl9ck= # =rAav # -----END PGP SIGNATURE----- # gpg: Signature made Tue 15 Jul 2025 15:44:05 EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-20250715' of https://github.com/philmd/qemu: system/runstate: Document qemu_add_vm_change_state_handler_prio* in hdr system/runstate: Document qemu_add_vm_change_state_handler() accel/hvf: Implement AccelClass::get_vcpu_stats() handler accel/tcg: Implement AccelClass::get_stats() handler accel/tcg: Propagate AccelState to dump_accel_info() accel/system: Add 'info accel' on human monitor accel/system: Introduce @x-accel-stats QMP command accel/tcg: Extract statistic related code to tcg-stats.c Revert "accel/tcg: Unregister the RCU before exiting RR thread" accel: Extract AccelClass definition to 'accel/accel-ops.h' accel: Rename 'system/accel-ops.h' -> 'accel/accel-cpu-ops.h' accel/tcg: Do not dump NaN statistics hw/core/machine: Display CPU model name in 'info cpus' command qapi/machine: Add @qom-type field to CpuInfoFast structure qapi/accel: Move definitions related to accelerators in their own file hw/arm/xen-pvh: Remove unnecessary 'hw/xen/arch_hvm.h' header hw/xen/arch_hvm: Unify x86 and ARM variants Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Conflicts: qapi/machine.json Commit 0462da9d6b19 ("qapi: remove trivial "Returns:" sections") removed trivial "Returns:". This caused a conflict with the move from machine.json to accelerator.json.
| * | hw/core/machine: Display CPU model name in 'info cpus' commandPhilippe Mathieu-Daudé2025-07-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the CPU model in 'info cpus'. Example before: $ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio QEMU 10.0.0 monitor - type 'help' for more information (qemu) info cpus * CPU #0: thread_id=42924 CPU #1: thread_id=42924 CPU #2: thread_id=42924 CPU #3: thread_id=42924 (qemu) q and after: $ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio QEMU 10.0.50 monitor - type 'help' for more information (qemu) info cpus * CPU #0: thread_id=42916 model=cortex-a72 CPU #1: thread_id=42916 model=cortex-a72 CPU #2: thread_id=42916 model=cortex-r5f CPU #3: thread_id=42916 model=cortex-r5f (qemu) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20250715090624.52377-3-philmd@linaro.org>
| * | qapi/machine: Add @qom-type field to CpuInfoFast structurePhilippe Mathieu-Daudé2025-07-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Knowing the QOM type name of a CPU can be useful, in particular to infer its model name. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20250715090624.52377-2-philmd@linaro.org>
| * | qapi/accel: Move definitions related to accelerators in their own filePhilippe Mathieu-Daudé2025-07-152-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Extract KVM definitions from machine.json to accelerator.json. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250703105540.67664-29-philmd@linaro.org>
| * | hw/arm/xen-pvh: Remove unnecessary 'hw/xen/arch_hvm.h' headerPhilippe Mathieu-Daudé2025-07-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "hw/xen/arch_hvm.h" only declares the arch_handle_ioreq() and arch_xen_set_memory() prototypes, which are not used by xen-pvh.c. Remove the unnecessary header inclusion. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-Id: <20250715071528.46196-1-philmd@linaro.org>
* | | Merge tag 'pull-vfio-20250715' of https://github.com/legoater/qemu into stagingStefan Hajnoczi2025-07-1613-21/+190
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vfio queue: * Fixed vfio-user issues reported by Coverity * Tweaked VFIO migration with multifd to support aarch64 * Introduced a property to override a device PCI class code # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmh2ciAACgkQUaNDx8/7 # 7KErLQ/+PyyV+lGPvqNzFaNL3w9LVDiCzppPZ5dIkJ7MuwFAgonltzQS/HpoGOLW # NMMJlDyBpilGO4pB8BGRL/Le4lZPQ+41zeCfOjG4q5cB9gYFAazj5356HOJNCsvH # xVeBINOrwcyqa5b31UN8gRsakcJjlBv7rSDhzGPedbjek7hmfYP9Y5EBr39yx5jU # Qw9WdI4Jxfwrz9pNkZstKNCHJDeSn8hwO4huAd6doC/Lno8rNleslALr+VdEfN7c # SaZ+opCiNGAowzD0Whg3wnsWa/wlczkPgcQ/qa3xH0D33AGhDXCJMDdNMXeZMBra # hjepQPPD8X6XXCBdRg7BavtxtjLAJSlghBTU5hZ+CJ/Pabyjhjh7rSmEcro2IvfL # ++ZAakwj3tj1sBYuT0u0C5eBeieSKroInz3r7zqLPyxeYDBvD+IPySxcqgA2w3cX # oJYgshQQHe4T4xdZKnWU2isWqkJ/X49sl7lIYCld1MgnGoZ/qEugmowsSzdnaJPG # Rq2T8G7tk/HYDQlGbNgEsBTeHJod1ZbNw00hs1DesbJLdT4OF0d5XzxvPIHHdsHc # 9N+NCLr22gMWBi1IMqM0X8Fx5rZYKiDChW2D9onnDXUEqXT5BI+5YYefIPFQJ2xy # fggbGXqKBfkUPoFlM8E19/dZSotgxyAS9wO3A3kx/z+J3+f24XI= # =Ns5P # -----END PGP SIGNATURE----- # gpg: Signature made Tue 15 Jul 2025 11:22:08 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250715' of https://github.com/legoater/qemu: vfio/migration: Max in-flight VFIO device state buffers size limit vfio/migration: Add x-migration-load-config-after-iter VFIO property vfio/pci: Introduce x-pci-class-code option hw/vfio-user: fix use of uninitialized variable hw/vfio-user: wait for proxy close correctly hw/vfio: fix region fd initialization hw/vfio-user: add Cédric Le Goater as a maintainer Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * | | vfio/migration: Max in-flight VFIO device state buffers size limitMaciej S. Szmigiero2025-07-152-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow capping the maximum total size of in-flight VFIO device state buffers queued at the destination, otherwise a malicious QEMU source could theoretically cause the target QEMU to allocate unlimited amounts of memory for buffers-in-flight. Since this is not expected to be a realistic threat in most of VFIO live migration use cases and the right value depends on the particular setup disable this limit by default by setting it to UINT64_MAX. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Avihai Horon <avihaih@nvidia.com> Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Link: https://lore.kernel.org/qemu-devel/4f7cad490988288f58e36b162d7a888ed7e7fd17.1752589295.git.maciej.szmigiero@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * | | vfio/migration: Add x-migration-load-config-after-iter VFIO propertyMaciej S. Szmigiero2025-07-158-1/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This property allows configuring whether to start the config load only after all iterables were loaded, during non-iterables loading phase. Such interlocking is required for ARM64 due to this platform VFIO dependency on interrupt controller being loaded first. The property defaults to AUTO, which means ON for ARM, OFF for other platforms. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Avihai Horon <avihaih@nvidia.com> Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Link: https://lore.kernel.org/qemu-devel/0e03c60dbc91f9a9ba2516929574df605b7dfcb4.1752589295.git.maciej.szmigiero@oracle.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * | | vfio/pci: Introduce x-pci-class-code optionTomita Moeko2025-07-153-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce x-pci-class-code option to allow users to override PCI class code of a device, similar to the existing x-pci-vendor-id option. Only the lower 24 bits of this option are used, though a uint32 is used here for determining whether the value is valid and set by user. Additionally, to ensure VGA ranges are only exposed on VGA devices, pci_register_vga() is now called in vfio_pci_config_setup(), after the class code override is completed. This is mainly intended for IGD devices that expose themselves either as VGA controller (primary display) or Display controller (non-primary display). The UEFI GOP driver depends on the device reporting a VGA controller class code (0x030000). Signed-off-by: Tomita Moeko <tomitamoeko@gmail.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250708145211.6179-1-tomitamoeko@gmail.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
| * | | hw/vfio-user: fix use of uninitialized variableJohn Levon2025-07-151-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coverity reported: CID 1611805: Uninitialized variables in vfio_user_dma_map(). This can occur in the happy path when ->async_ops was not set; as this doesn't typically happen, it wasn't caught during testing. Align both map and unmap implementations to initialize ret the same way to resolve this. Resolves: Coverity CID 1611805 Fixes: 18e899e6 ("vfio-user: implement VFIO_USER_DMA_MAP/UNMAP") Reported-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Link: https://lore.kernel.org/qemu-devel/20250715115954.515819-5-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>