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path: root/include/exec/exec-all.h (follow)
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* include/exec: Remove CODE_GEN_AVG_BLOCK_SIZERichard Henderson2023-06-051-10/+0
* tcg: Spit out exec/translation-block.hRichard Henderson2023-06-051-131/+1
* exec-all: Widen TranslationBlock pc and cs_base to 64-bitsRichard Henderson2023-06-051-2/+2
* exec-all: Widen tb_page_addr_t for user-onlyRichard Henderson2023-06-051-2/+2
* tcg: remove the final vestiges of dstateAlex Bennée2023-06-011-3/+0
* tcg: Remove DEBUG_DISASRichard Henderson2023-05-231-3/+0
* accel/tcg: Pass last not end to tb_invalidate_phys_rangeRichard Henderson2023-03-281-1/+1
* includes: move tb_flush into its own headerAlex Bennée2023-03-071-1/+0
* include/exec: Remove `tb_pc()`Anton Johansson2023-03-011-7/+0
* include/exec: Replace `TARGET_TB_PCREL` with `CF_PCREL`Anton Johansson2023-03-011-16/+11
* include/exec: Introduce `CF_PCREL`Anton Johansson2023-03-011-0/+1
* accel/tcg: Add 'size' param to probe_access_fullRichard Henderson2023-02-281-1/+1
* accel/tcg: Add 'size' param to probe_access_flags()Daniel Henrique Barboza2023-02-281-1/+2
* bsd-user/mmap: use TSA_NO_TSA to suppress clang TSA warnings in FreeBSDEmanuele Giuseppe Esposito2023-02-171-2/+3
* tcg: Add TranslationBlock.jmp_insn_offsetRichard Henderson2023-01-171-1/+2
* tcg: Rename TB_JMP_RESET_OFFSET_INVALID to TB_JMP_OFFSET_INVALIDRichard Henderson2023-01-171-1/+1
* accel/tcg: Use interval tree for TBs in user-only modeRichard Henderson2022-12-201-3/+40
* accel/tcg: Remove will_exit argument from cpu_restore_stateRichard Henderson2022-11-011-4/+1
* accel/tcg: Introduce cpu_unwind_state_dataRichard Henderson2022-11-011-4/+17
* accel/tcg: Remove restore_state_to_opc functionRichard Henderson2022-10-261-3/+0
* accel/tcg: Add restore_state_to_opc to TCGCPUOpsRichard Henderson2022-10-261-1/+1
* accel/tcg: Unify declarations of tb_invalidate_phys_rangeRichard Henderson2022-10-261-1/+1
* accel/tcg: Introduce tb_{set_}page_addr{0,1}Richard Henderson2022-10-261-0/+22
* accel/tcg: Move assert_no_pages_locked to internal.hRichard Henderson2022-10-261-8/+0
* accel/tcg: Introduce TARGET_TB_PCRELRichard Henderson2022-10-041-2/+30
* accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-0/+6
* accel/tcg: Introduce tlb_set_page_fullRichard Henderson2022-10-031-0/+22
* accel/tcg: Introduce probe_access_fullRichard Henderson2022-10-031-0/+15
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-1/+0
* accel/tcg: Make tb_htable_lookup staticRichard Henderson2022-09-061-3/+0
* accel/tcg: Properly implement get_page_addr_code for user-onlyRichard Henderson2022-09-061-53/+24
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-10/+10
* exec/cpu: Make address_space_init/reloading_memory_map target agnosticPhilippe Mathieu-Daudé2022-03-061-25/+0
* misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé2022-03-061-1/+0
* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-211-2/+0
* accel/tcg: introduce CF_NOIRQAlex Bennée2021-11-291-0/+1
* linux-user: Add cpu_loop_exit_sigbusRichard Henderson2021-11-021-0/+14
* linux-user: Add cpu_loop_exit_sigsegvRichard Henderson2021-11-021-0/+15
* linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDERRichard Henderson2021-11-021-12/+0
* accel/tcg: Split out handle_sigsegv_accerr_writeRichard Henderson2021-10-301-0/+12
* accel/tcg: Split out adjust_signal_pcRichard Henderson2021-10-301-0/+10
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-211-0/+13
* accel/tcg: Record singlestep_enabled in tb->cflagsRichard Henderson2021-07-211-0/+1
* accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTRRichard Henderson2021-07-211-7/+9
* accel/tcg: Move curr_cflags into cpu-exec.cRichard Henderson2021-07-211-4/+1
* accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNSRichard Henderson2021-07-211-1/+3
* accel/tcg: Reduce 'exec/tb-context.h' inclusionPhilippe Mathieu-Daudé2021-05-261-1/+0
* accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()Richard Henderson2021-05-251-0/+12
* accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus()Richard Henderson2021-05-251-0/+13
* accel/tcg: Add tlb_flush_range_by_mmuidx()Richard Henderson2021-05-251-0/+19