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* include/hw/ppc include/hw/pci-host: Drop extra typedefsMarkus Armbruster2023-01-202-3/+0
| | | | | | | | | | | PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221222104628.659681-5-armbru@redhat.com>
* include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.hMarkus Armbruster2023-01-201-1/+2
| | | | | | | | | | The next commit needs to include hw/ppc/pnv.h from hw/pci-host/pnv_phb.h. Avoid an inclusion loop. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221222104628.659681-4-armbru@redhat.com>
* hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in headerPhilippe Mathieu-Daudé2023-01-131-0/+18
| | | | | | | | | Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a header to be able to access it from board code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-8-philmd@linaro.org>
* include/hw/pci: Split pci_device.h off pci.hMarkus Armbruster2023-01-084-4/+4
| | | | | | | | | | | | | | | | | | | PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* include/hw/pci: Break inclusion loop pci_bridge.h and cxl.hMarkus Armbruster2023-01-086-11/+2
| | | | | | | | | | | | | hw/pci/pci_bridge.h and hw/cxl/cxl.h include each other. Fortunately, breaking the loop is merely a matter of deleting unnecessary includes from headers, and adding them back in places where they are now missing. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-2-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/intc/loongarch_pch: Change default irq number of pch irq controllerTianrui Zhao2023-01-061-0/+1
| | | | | | | | | | | | Change the default irq number of pch pic to 32, so that the irq number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM' macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard format. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230104020518.2564263-4-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/intc/loongarch_pch_msi: add irq number propertyTianrui Zhao2023-01-061-1/+0
| | | | | | | | | | This patch adds irq number property for loongarch msi interrupt controller, and remove hard coding irq number macro. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/loongarch: Improve fdt for LoongArch virt machineXiaojuan Yang2022-11-041-0/+1
| | | | | | | | | Add new items into LoongArch FDT, including rtc and uart info. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* hw/ppc/mac.h: Move grackle-pcihost type declaration out to a headerBALATON Zoltan2022-10-311-0/+44
| | | | | | | Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <b133a84dfd38366eea2bb11b7ca433758efacc10.1666957578.git.balaton@eik.bme.hu> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* hw/loongarch: Add platform bus supportXiaojuan Yang2022-09-201-0/+5
| | | | | | | | | | Add platform bus support and add the bus information such as address, size, irq number to FDT table. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20220908094623.73051-5-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* ppc/pnv: add phb-id/chip-id PnvPHB4RootBus propertiesDaniel Henrique Barboza2022-08-311-0/+10
| | | | | | | | | | | | | | | | | | | | | The same rationale provided in the PHB3 bus case applies here. Note: we could have merged both buses in a single object, like we did with the root ports, and spare some boilerplate. The reason we opted to preserve both buses objects is twofold: - there's not user side advantage in doing so. Unifying the root ports presents a clear user QOL change when we enable user created devices back. The buses objects, aside from having a different QOM name, is transparent to the user; - we leave a door opened in case we want to increase the root port limit for phb4/5 later on without having to deal with phb3 code. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220811163950.578927-3-danielhb413@gmail.com>
* ppc/pnv: add phb-id/chip-id PnvPHB3RootBus propertiesDaniel Henrique Barboza2022-08-311-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | We rely on the phb-id and chip-id, which are PHB properties, to assign chassis and slot to the root port. For default devices this is no big deal: the root port is being created under pnv_phb_realize() and the values are being passed on via the 'index' and 'chip-id' of the pnv_phb_attach_root_port() helper. If we want to implement user created root ports we have a problem. The user created root port will not be aware of which PHB it belongs to, unless we're willing to violate QOM best practices and access the PHB via dev->parent_bus->parent. What we can do is to access the root bus parent bus. Since we're already assigning the root port as QOM child of the bus, and the bus is initiated using PHB properties, let's add phb-id and chip-id as properties of the bus. This will allow us trivial access to them, for both user-created and default root ports, without doing anything too shady with QOM. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220811163950.578927-2-danielhb413@gmail.com>
* ppc/pnv: remove PnvPHB4.versionDaniel Henrique Barboza2022-08-311-2/+0
| | | | | | | | It's unused. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-12-danielhb413@gmail.com>
* ppc/pnv: remove pecc->rp_modelDaniel Henrique Barboza2022-08-311-1/+0
| | | | | | | | The attribute is unused. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-11-danielhb413@gmail.com>
* ppc/pnv: remove pnv-phb4-root-portDaniel Henrique Barboza2022-08-311-9/+0
| | | | | | | | | | The unified pnv-phb-root-port can be used instead. The phb4-root-port device isn't exposed to the user in any official QEMU release so there's no ABI breakage in removing it. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-9-danielhb413@gmail.com>
* ppc/pnv: remove pnv-phb3-root-portDaniel Henrique Barboza2022-08-311-6/+0
| | | | | | | | | | The unified pnv-phb-root-port can be used in its place. There is no ABI breakage in doing so because no official QEMU release introduced user creatable pnv-phb3-root-port devices. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-8-danielhb413@gmail.com>
* ppc/pnv: turn PnvPHB4 into a PnvPHB backendDaniel Henrique Barboza2022-08-311-1/+4
| | | | | | | | | | | | | | | | | | | | Change the parent type of the PnvPHB4 device to TYPE_PARENT since the PCI bus is going to be initialized by the PnvPHB parent. Functions that needs to access the bus via a PnvPHB4 object can do so via the phb4->phb_base pointer. pnv_phb4_pec now creates a PnvPHB object. The powernv9 machine class will create PnvPHB devices with version '4'. powernv10 will create using version '5'. Both are using global machine properties in their class_init() to do that. These changes will benefit us when adding PnvPHB user creatable devices for powernv9 and powernv10. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-6-danielhb413@gmail.com>
* ppc/pnv: add PHB4 bus init helperDaniel Henrique Barboza2022-08-311-0/+1
| | | | | | | | | | Similar to what we already did for the PnvPHB3 device, let's add a helper to init the bus when using a PnvPHB4. This helper will be used by PnvPHb when PnvPHB4 turns into a backend. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-5-danielhb413@gmail.com>
* ppc/pnv: turn PnvPHB3 into a PnvPHB backendDaniel Henrique Barboza2022-08-311-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | We need a handful of changes that needs to be done in a single swoop to turn PnvPHB3 into a PnvPHB backend. In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a couple of instances in pnv_phb3.c that needs to access the PCI bus, so a phb_base pointer is added to allow access to the parent PnvPHB. The PnvPHB3 root port will now be connected to a PnvPHB object. In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3 backend from the PnvPHB child. A global property is added in pnv_machine_power8_class_init() to ensure that all PnvPHBs are created with phb->version = 3. After all these changes we're still able to boot a powernv8 machine with default settings. The real gain will come with user created PnvPHB devices, coming up next. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-4-danielhb413@gmail.com>
* ppc/pnv: add PHB3 bus init helperDaniel Henrique Barboza2022-08-311-0/+1
| | | | | | | | | | | | | | | The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio regions, registering it via pci_register_root_bus() and then setup the iommu. We'll want to init the bus from outside pnv_phb3.c when the bus is removed from the PnvPHB3 device and put into a new parent PnvPHB device. The new pnv_phb3_bus_init() helper will be used by the parent to init the bus when using the PHB3 backend. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-2-danielhb413@gmail.com>
* hw/loongarch: Change macro name 'LS7A_XXX' to 'VIRT_XXX'Xiaojuan Yang2022-07-291-23/+20
| | | | | | | | | | Change macro name 'LS7A_XXX' to 'VIRT_XXX', as the loongarch virt machinue use the GPEX bridge instead of LS7A bridge. So the macro name should keep consistency. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220729073018.27037-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* i386/pc: create pci-host qdev prior to pc_memory_init()Joao Martins2022-07-261-1/+2
| | | | | | | | | | | | | | | | | | | At the start of pc_memory_init() we usually pass a range of 0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or 32G (q35). To get the real user value, we need to get pci-host passed property for default pci_hole64_size. Thus to get that, create the qdev prior to memory init to better make estimations on max used/phys addr. This is in preparation to determine that host-phys-bits are enough and also for pci-hole64-size to be considered to relocate ram-above-4g to be at 1T (on AMD platforms). Signed-off-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220719170014.27028-3-joao.m.martins@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* hw/loongarch: Add acpi ged supportXiaojuan Yang2022-07-191-0/+4
| | | | | | | | | | | | | | Loongarch virt machine uses general hardware reduces acpi method, rather than LS7A acpi device. Now only power management function is used in acpi ged device, memory hotplug will be added later. Also acpi tables such as RSDP/RSDT/FADT etc. The acpi table has submited to acpi spec, and will release soon. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220712083206.4187715-6-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* ppc: Define SETFIELD for the ppc targetAlexey Kardashevskiy2022-07-061-16/+0
| | | | | | | | | | | | | It keeps repeating, move it to the header. This uses __builtin_ffsll() to allow using the macros in #define. This is not using the QEMU's FIELD macros as this would require changing all such macros found in skiboot (the PPC PowerNV firmware). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220628080544.1509428-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
* hw/pci-host/i440fx: Remove unused parameter from i440fx_init()Bernhard Beschow2022-06-281-1/+0
| | | | | | | | | pi440fx_state is an out-parameter which is never read by the caller. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220612192800.40813-1-shentey@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* hw/loongarch: Add LoongArch ls7a rtc device supportXiaojuan Yang2022-06-061-0/+4
| | | | | | | | | | This patch add ls7a rtc device support. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-39-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/loongarch: Add some devices support for 3A5000.Xiaojuan Yang2022-06-061-0/+7
| | | | | | | | | | | | | | 1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the pci host. Non pci device use irq 0-16, pci device use 16-64. 3.Add some unimplented device to emulate guest unused memory space. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-38-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)Xiaojuan Yang2022-06-061-0/+3
| | | | | | | | | | This patch realize PCH-MSI interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)Xiaojuan Yang2022-06-061-0/+30
| | | | | | | | | | This patch realize the PCH-PIC interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-33-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Clean up header guards that don't match their file nameMarkus Armbruster2022-05-111-2/+2
| | | | | | | | | | | | | Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-2-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [Change to generated file ebpf/rss.bpf.skeleton.h backed out]
* dino: move from hw/hppa to hw/pci-hostMark Cave-Ayland2022-05-081-0/+146
| | | | | | | | | | | Move the DINO device implementation from hw/hppa to hw/pci-host so that it is located with all the other PCI host bridges. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220504092600.10048-23-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* ppc/pnv: Fix number of registers in the PCIe controller on POWER9Frederic Barrat2022-04-041-1/+1
| | | | | | | | | | | | | | | | The spec defines 3 registers, even though only index 0 and 2 are valid on POWER9. The same model is used on POWER10. Register 1 is defined there but we currently don't use it in skiboot. So we can keep reporting an error on write. Reported by Coverity (CID 1487176). Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge") Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: Introduce a pnv-phb5 device to match root portFrederic Barrat2022-03-141-0/+5
| | | | | | | | | | | | | | | | | | | | We already have the pnv-phb3 and pnv-phb4 devices for POWER8 and POWER9 respectively. POWER10 uses version 5 of the PHB. It is very close to the PHB4 from POWER9, at least in our model and we could almost keep using the PHB4 model. However the matching root port pnv-phb5-root-port is specific to POWER10 so to avoid confusion as well as making it easy to introduce differences later, we create a pnv-phb5 class, which is mostly an alias for pnv-phb4 for now. With this patch, the command line for a user-created PHB on powernv10 becomes: -machine powernv10 -nodefaults -device pnv-phb5 -device pnv-phb5-root-port Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220310155101.294568-2-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: Add support for PHB5 "Address-based trigger" modeCédric Le Goater2022-03-021-0/+2
| | | | | | | | | | When the Address-Based Interrupt Trigger mode is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB directly triggers the IC ESB page of the interrupt number and not the notify page of the IC anymore. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: Add support for PQ offload on PHB5Cédric Le Goater2022-03-021-0/+1
| | | | | | | | | | | | | | | | | The PQ_disable configuration bit disables the check done on the PQ state bits when processing new MSI interrupts. When bit 9 is enabled, the PHB forwards any MSI trigger to the XIVE interrupt controller without checking the PQ state bits. The XIVE IC knows from the trigger message that the PQ bits have not been checked and performs the check locally. This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level. PQ_disable enablement is a requirement for StoreEOI. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridgeCédric Le Goater2022-03-021-0/+12
| | | | | | | PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: Add a 'rp_model' class attribute for the PHB4 PECCédric Le Goater2022-01-181-0/+1
| | | | | | | | | PHB5 will introduce its own root port model. Prepare ground for it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220117122753.1655504-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: remove PnvPhb4PecStack objectDaniel Henrique Barboza2022-01-181-17/+0
| | | | | | | | | | | All the complexity that was scattered between PnvPhb4PecStack and PnvPHB4 are now centered in the PnvPHB4 device. PnvPhb4PecStack does not serve any purpose in the current code base. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220114180719.52117-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: make PECs create and realize PHB4sDaniel Henrique Barboza2022-01-181-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the design of the PEC device to create and realize PHB4s instead of PecStacks. After all the recent changes, PHB4s now contain all the information needed for their proper functioning, not relying on PecStack in any capacity. All changes are being made in a single patch to avoid renaming parts of the PecState and leaving the code in a strange way. E.g. rename PecClass->num_stacks to num_phbs, which would then read a pnv_pec_num_stacks[] array. To avoid mixing the old and new design more than necessary it's clearer to do these changes in a single step. The name changes made are: - in PnvPhb4PecState: * rename 'num_stacks' to 'num_phbs' * remove the pec->stacks[] array. Current code relies on the pec->stacks[] obj acting as a simple container, without ever accessing pec->stacks[] for any other purpose. Instead of converting this into a pec->phbs[] array, remove it - in PnvPhb4PecClass, rename *num_stacks to *num_phbs; - pnv_pec_num_stacks[] is renamed to pnv_pec_num_phbs[]. The logical changes: - pnv_pec_default_phb_realize(): * init and set the properties of the PnvPHB4 qdev * do not use stack->phb anymore; - pnv_pec_realize(): * use the new default_phb_realize() to init/realize each PHB if running with defaults; - pnv_pec_instance_init(): removed since we're creating the PHBs during pec_realize(); - pnv_phb4_get_stack(): * renamed to pnv_phb4_get_pec() and returns a PnvPhb4PecState*; - pnv_phb4_realize(): use 'phb->pec' instead of 'stack'. This design change shouldn't caused any behavioral change in the runtime of the machine. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220114180719.52117-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: remove PnvPhb4PecStack::stack_noDaniel Henrique Barboza2022-01-181-3/+0
| | | | | | | | | | pnv_pec_default_phb_realize() stopped using it after the previous patch and no one else is using it. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220114180719.52117-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: remove stack pointer from PnvPHB4Daniel Henrique Barboza2022-01-181-2/+0
| | | | | | | | | | | | | | | | | This pointer was being used for two reasons: pnv_phb4_update_regions() was using it to access the PHB and phb4_realize() was using it as a way to determine if the PHB was user created. We can determine if the PHB is user created via phb->pec, introduced in the previous patch, and pnv_phb4_update_regions() is no longer using stack->phb. Remove the pointer from the PnvPHB4 device. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220114180719.52117-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: introduce PnvPHB4 'pec' propertyDaniel Henrique Barboza2022-01-181-0/+3
| | | | | | | | | | | This property will track the owner PEC of this PHB. For now it's redundant since we can retrieve the PEC via phb->stack->pec but it will not be redundant when we get rid of the stack device. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220114180719.52117-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move phb_regs_mr to PnvPHB4Daniel Henrique Barboza2022-01-181-3/+3
| | | | | | | | | | After recent changes, this MemoryRegion can be migrated to PnvPHB4 without too much trouble. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-11-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move nest_regs_mr to PnvPHB4Daniel Henrique Barboza2022-01-181-2/+1
| | | | | | | | | | | | | | | | | | | | We're now able to cleanly move nest_regs_mr to the PnvPHB4 device. One thing of notice here is the need to use a phb->stack->pec pointer because pnv_pec_stk_nest_xscom_write requires a PEC object. Another thing that can be noticed in the use of 'stack->stack_no' that still remains throughout the XSCOM code. After moving all MemoryRegions to the PnvPHB4 object, this illustrates what is the remaining role of the stack: provide a PEC pointer and the 'stack_no' information. If we can provide these in the PnvPHB4 object instead (spoiler: we can, and we will), the PnvPhb4PecStack device will be deprecated and can be removed. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-10-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move nest_regs[] to PnvPHB4Daniel Henrique Barboza2022-01-181-3/+4
| | | | | | | | | | | | | | stack->nest_regs[] is used in several XSCOM functions and it's one of the main culprits of having to deal with stack->phb pointers around the code. Sure, we're having to add 2 extra stack->phb pointers to ease nest_regs[] migration to PnvPHB4. They'll be dealt with shortly. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move mmbar0/mmbar1 and friends to PnvPHB4Daniel Henrique Barboza2022-01-181-8/+6
| | | | | | | | | | | These 2 MemoryRegions, together with mmio(0|1)_base and mmio(0|1)_size variables, are used together in the same functions. We're better of moving them all in a single step. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move intbar to PnvPHB4Daniel Henrique Barboza2022-01-181-1/+1
| | | | | | | | | This MemoryRegion can also be moved in a single step. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move phbbar to PnvPHB4Daniel Henrique Barboza2022-01-181-1/+3
| | | | | | | | | | | | | This MemoryRegion is simple enough to be moved in a single step. A 'stack->phb' pointer had to be introduced in pnv_pec_stk_update_map() because this function isn't ready to be fully converted to use a PnvPHB4 pointer instead. This will be dealt with in the following patches. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: move PCI registers to PnvPHB4Daniel Henrique Barboza2022-01-181-5/+5
| | | | | | | | | | | | Previous patch changed pnv_pec_stk_pci_xscom_read() and pnv_pec_stk_pci_xscom_write() to use a PnvPHB4 opaque, making it easier to move both pci_regs[] and the pci_regs_mr MemoryRegion to the PnvHB4 object. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
* ppc/pnv: turn pnv_phb4_update_regions() into staticDaniel Henrique Barboza2022-01-121-1/+0
| | | | | | | | | Its only callers are inside pnv_phb4.c. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220111131027.599784-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>