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* hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé2025-10-071-17/+0
| | | | | | | | | | | | When removing the spitz and tosa board, commit b62151489ae ("hw/arm: Remove deprecated akita, borzoi spitz, terrier, tosa boards") removed the last calls to sl_bootparam_write(). Remove it, along with the "hw/arm/sharpsl.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20251001084047.67423-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2025-10-071-0/+4
| | | | | | | | | | This wires a second GIC for the Cortex-R5, all the IRQs are split when there is an RPU instanciated. Signed-off-by: Clément Chigot <chigot@adacore.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-4-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2025-10-071-0/+1
| | | | | | | | | | | | This define will be needed in a later patch in XlnxZynqMPState structure, hence move it within xlnx-zynqmp header. Add XLXN_ZYNQMP prefix as it's now public. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20250930115718.437100-2-chigot@adacore.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: add versal2 SoCLuc Michel2025-10-071-1/+16
| | | | | | | | | | | | | | | | | | | | Add the Versal Gen 2 (versal2) version of the Versal SoC family. This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters) and 10 Cortex-R52 cores (split into 5 clusters). The similarities between versal and versal2 in term of architecture allow to reuse the VersalMap structure to almost fully describe the implemented parts of versal2. The versal2 eFuse device differs quite a lot from the versal one and is left as future work. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-41-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel2025-10-072-0/+330
| | | | | | | | | | | | | Add the versal2 version of the CRL device. For the implemented part, it is similar to the versal version but drives reset line of more devices. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-37-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: tidy upLuc Michel2025-10-071-204/+0
| | | | | | | | | | | | | | Remove now unused macros in xlnx-versal.[ch]. Those macros have been replaced by the VersalMap structure that serves as a central description for the SoC. The ones still in use in the versal_unimp function are inlined. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-36-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2025-10-071-6/+0
| | | | | | | | | | | | | Use the bsa.h header for ARM timer and maintainance IRQ indices instead of redefining our owns. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-35-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2025-10-071-4/+4
| | | | | | | | | | | | | | | | Refactor the device reset logic to have a common register write callback for all the devices. This uses a decode function to map the register address to the actual peripheral to reset. This refactoring changes the CPU property name from cpu_r5[*] to rpu[*] to ease with the connections in the Versal SoC. It also fixes a bug where the gem device pointer was mapped to the usb link property. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-33-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2025-10-071-2/+29
| | | | | | | | | | | | Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-32-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel2025-10-071-0/+1
| | | | | | | | | | | | Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the number of CPUs in the SoC. Use it in the xlnx-versal-virt machine. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-30-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: ddr: refactor creationLuc Michel2025-10-071-5/+2
| | | | | | | | | | | | | | Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-29-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2025-10-071-4/+0
| | | | | | | | | | | Refactor the OCM creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-28-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: rpu: refactor creationLuc Michel2025-10-071-11/+0
| | | | | | | | | | | | Refactor the RPU cluster creation using the VersalMap structure. This effectively instantiate the RPU GICv2 which was not instantiated before. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-27-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2025-10-071-0/+1
| | | | | | | | | | | | | | | | | | | The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-25-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias2025-10-071-0/+1
| | | | | | | | | | | | | | | | | | Introduce a 'first-cpu-index' property for specifying the first QEMU CPU connected to the GICv3. This makes it possible to have multiple instances of the GICv3 connected to different CPU clusters. For KVM, mark this property has unsupported. It probably does not make much sense as it is intented to be used to model non-SMP systems. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-24-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: refactor CPU cluster creationLuc Michel2025-10-071-10/+2
| | | | | | | | | | | | | | | Refactor the CPU cluster creation using the VersalMap structure. There is no functional change. The clusters properties are now described in the VersalMap structure. For now only the APU is converted. The RPU will be taken care of by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-21-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal-virt: virtio: refactor creationLuc Michel2025-10-071-0/+3
| | | | | | | | | | | | | Refactor the creation of virtio devices. Use the accessors provided by the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are defined in the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-20-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: crl: refactor creationLuc Michel2025-10-071-3/+0
| | | | | | | | | | | | | Refactor the CRL device creation using the VersalMap structure. The connections to the RPU CPUs are temporarily removed and will be reintroduced with next refactoring commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-19-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: cfu: refactor creationLuc Michel2025-10-071-14/+0
| | | | | | | | | | | | | Refactor the CFU device creation using the VersalMap structure. All users of the APB IRQ OR gate have now been converted. The OR gate device can be dropped. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-18-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: rtc: refactor creationLuc Michel2025-10-071-2/+0
| | | | | | | | | | | | | | | Refactor the RTC device creation using the VersalMap structure. The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1 (addr error IRQ). This does not change the current behaviour since the RTC model does not implement those IRQs anyway. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-17-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: trng: refactor creationLuc Michel2025-10-071-2/+0
| | | | | | | | | | | Refactor the TRNG device creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-16-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: bbram: refactor creationLuc Michel2025-10-071-2/+1
| | | | | | | | | | | | | | | Refactor the BBRAM device creation using the VersalMap structure. Note that the corresponding FDT node is removed. It does not correspond to any real node in standard Versal DTBs. No matching drivers exist for it. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-15-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: PMC IOU SCLR: refactor creationLuc Michel2025-10-071-5/+0
| | | | | | | | | | | | | Refactor the PMC IOU SLCR device creation using the VersalMap structure. This is the first user of a shared IRQ using an OR gate. The OSPI controller is reconnected to the SLCR. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-14-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: ospi: refactor creationLuc Michel2025-10-071-10/+2
| | | | | | | | | | | | | | Refactor the OSPI controller creation using the VersalMap structure. Note that the connection to the PMC IOU SLCR is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-12-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: efuse: refactor creationLuc Michel2025-10-071-4/+1
| | | | | | | | | | | | | | | Refactore the eFuse devices creation using the VersalMap structure. Note that the corresponding FDT nodes are removed. They do not correspond to any real node in standard Versal DTBs. No matching drivers exist for them. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-11-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: usb: refactor creationLuc Michel2025-10-071-5/+0
| | | | | | | | | | | | | | Refactor the USB controller creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-10-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: xram: refactor creationLuc Michel2025-10-071-6/+0
| | | | | | | | | | | Refactor the XRAM devices creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-9-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: adma: refactor creationLuc Michel2025-10-071-2/+0
| | | | | | | | | | | | | | Refactor the ADMA creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-8-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: gem: refactor creationLuc Michel2025-10-071-3/+0
| | | | | | | | | | | | | | | | | | | Refactor the GEM ethernet controllers creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. The FDT nodes are created in reverse order compared to the devices creation to keep backward compatibility with the previous generated FDTs. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-7-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: sdhci: refactor creationLuc Michel2025-10-071-2/+3
| | | | | | | | | | | Refactor the SDHCI controllers creation using the VersalMap structure. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-6-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: canfd: refactor creationLuc Michel2025-10-071-3/+4
| | | | | | | | | | | | | | | | | | | Refactor the CAN controllers creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. The xlnx-versal-virt machine now dynamically creates the correct amount of CAN bus link properties based on the number of CAN controller advertised by the SoC. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-5-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: uart: refactor creationLuc Michel2025-10-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | Refactor the UARTs creations. The VersalMap struct is now used to describe the SoC and its peripherals. For now it contains the two UARTs mapping information. The creation function now embeds the FDT creation logic as well. The devices are now created dynamically using qdev_new and (qdev|sysbus)_realize_and_unref. This will allow to rely entirely on the VersalMap structure to create the SoC and allow easy addition of new SoCs of the same family (like versal2 coming with next commits). Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-4-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: prepare for FDT creationLuc Michel2025-10-071-0/+12
| | | | | | | | | | | | | | | | | The following commits will move FDT creation logic from the xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by passing the FDT handle to the SoC before it is realized. For now the SoC only creates the two clock nodes. The ones from the xlnx-versal virt machine are renamed with a `old-' prefix and will be removed once they are not referenced anymore. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-3-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* hw/arm/xlnx-versal: split the xlnx-versal typeLuc Michel2025-10-072-1/+26
| | | | | | | | | | | | | | | | | Split the xlnx-versal device into two classes, a base, abstract class and the existing concrete one. Introduce a VersalVersion type that will be used across several device models when versal2 implementation is added. This is in preparation for versal2 implementation. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250926070806.292065-2-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson2025-10-0619-32/+243
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging virtio,pci,pc: features, fixes users can now control VM bit in smbios. vhost-user-device is now user-createable. intel_iommu now supports PRI virtio-net now supports GSO over UDP tunnel ghes now supports error injection amd iommu now supports dma remapping for vfio better error messages for virtio small fixes all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmji0s0PHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpuH4H/09h70IqAWZGHIWKGmmGGtdKOj3g54KuI0Ss # mGECEsHvvBexOy670Qy8jdgXfaW4UuNui8BiOnJnGsBX8Y0dy+/yZori3KhkXkaY # D57Ap9agkpHem7Vw0zgNsAF2bzDdlzTiQ6ns5oDnSq8yt82onCb5WGkWTGkPs/jL # Gf8Jv+Ddcpt5SU4/hHPYC8pUhl7z4xPOOyl0Qp1GG21Pxf5v4sGFcWuGGB7UEPSQ # MjZeoM0rSnLDtNg18sGwD5RPLQs13TbtgsVwijI79c3w3rcSpPNhGR5OWkdRCIYF # 8A0Nhq0Yfo0ogTht7yt1QNPf/ktJkuoBuGVirvpDaix2tCBECes= # =Zvq/ # -----END PGP SIGNATURE----- # gpg: Signature made Sun 05 Oct 2025 01:19:25 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [unknown] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (75 commits) virtio: improve virtqueue mapping error messages pci: Fix wrong parameter passing to pci_device_get_iommu_bus_devfn() intel_iommu: Simplify caching mode check with VFIO device intel_iommu: Enable Enhanced Set Root Table Pointer Support (ESRTPS) vdpa-dev: add get_vhost() callback for vhost-vdpa device amd_iommu: HATDis/HATS=11 support intel-iommu: Move dma_translation to x86-iommu amd_iommu: Refactor amdvi_page_walk() to use common code for page walk amd_iommu: Do not assume passthrough translation when DTE[TV]=0 amd_iommu: Toggle address translation mode on devtab entry invalidation amd_iommu: Add dma-remap property to AMD vIOMMU device amd_iommu: Set all address spaces to use passthrough mode on reset amd_iommu: Toggle memory regions based on address translation mode amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL amd_iommu: Add replay callback amd_iommu: Unmap all address spaces under the AMD IOMMU on reset amd_iommu: Use iova_tree records to determine large page size on UNMAP amd_iommu: Sync shadow page tables on page invalidation amd_iommu: Add basic structure to support IOMMU notifier updates amd_iommu: Add a page walker to sync shadow page tables on invalidation ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| * virtio: improve virtqueue mapping error messagesAlessandro Ratti2025-10-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve error reporting when virtqueue ring mapping fails by including a device identifier in the error message. Introduce a helper qdev_get_printable_name() in qdev-core, which returns either: - the device ID, if explicitly provided (e.g. -device ...,id=foo) - the QOM path from qdev_get_dev_path(dev) otherwise - "<unknown device>" as a fallback when no identifier is present This makes it easier to identify which device triggered the error in multi-device setups or when debugging complex guest configurations. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/230 Buglink: https://bugs.launchpad.net/qemu/+bug/1919021 Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alessandro Ratti <alessandro@0x65c.net> Message-Id: <20250924093138.559872-2-alessandro@0x65c.net> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * intel-iommu: Move dma_translation to x86-iommuJoao Martins2025-10-051-0/+1
| | | | | | | | | | | | | | | | | | | | To be later reused by AMD, now that it shares similar property. Signed-off-by: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250919213515.917111-22-alejandro.j.jimenez@oracle.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * virtio: unify virtio_notify_irqfd() and virtio_notify()Stefan Hajnoczi2025-10-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The difference between these two functions: - virtio_notify() uses the interrupt code path (MSI or classic IRQs) - virtio_notify_irqfd() uses guest notifiers (irqfds) virtio_notify() can only be called with the BQL held because the interrupt code path requires the BQL. Device models use virtio_notify_irqfd() from IOThreads since the BQL is not held. The two functions can be unified by pushing down the if (qemu_in_iothread()) check from virtio-blk and virtio-scsi into core virtio code. This is in preparation for the next commit that will add irqfd support to virtio_notify_config() and where it's unattractive to introduce another irqfd-only API for device model callers. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250922220149.498967-3-stefanha@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * x86: ich9: fix default value of 'No Reboot' bit in GCSIgor Mammedov2025-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [2] initialized 'No Reboot' bit to 1 by default. And due to quirk it happened to work with linux iTCO_wdt driver (which clears it on module load). However spec [1] states: " R/W. This bit is set when the “No Reboot” strap (SPKR pin on ICH9) is sampled high on PWROK. " So it should be set only when '-global ICH9-LPC.noreboot=true' and cleared when it's false (which should be default). Fix it to behave according to spec and set 'No Reboot' bit only when '-global ICH9-LPC.noreboot=true'. 1) Intel I/O Controller Hub 9 (ICH9) Family Datasheet (rev: 004) 2) Fixes: 920557971b6 (ich9: add TCO interface emulation) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250922132600.562193-1-imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * intel_iommu: Add PRI operations supportCLEMENT MATHIEU--DRIF2025-10-051-0/+1
| | | | | | | | | | | | | | | | | | Implement the PRI callbacks in vtd_iommu_ops. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901111630.1018573-6-clement.mathieu--drif@eviden.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * pcie: Add a way to get the outstanding page request allocation (pri) from ↵CLEMENT MATHIEU--DRIF2025-10-051-0/+1
| | | | | | | | | | | | | | | | | | the config space. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901111630.1018573-2-clement.mathieu--drif@eviden.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/virtio: rename vhost-user-device and make user creatableAlex Bennée2025-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We didn't make the device user creatable in the first place because we were worried users might get confused. Rename the device to make its nature as a test device even more explicit. While we are at it add a Kconfig variable so it can be skipped for those that want to thin out their build configuration even further. Acked-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250820195632.1956795-1-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901105948.982583-1-alex.bennee@linaro.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * pcie_sriov: Fix broken MMIO accesses from SR-IOV VFsDamien Bergamini2025-10-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with commit cab1398a60eb, SR-IOV VFs are realized as soon as pcie_sriov_pf_init() is called. Because pcie_sriov_pf_init() must be called before pcie_sriov_pf_init_vf_bar(), the VF BARs types won't be known when the VF realize function calls pcie_sriov_vf_register_bar(). This breaks the memory regions of the VFs (for instance with igbvf): $ lspci ... Region 0: Memory at 281a00000 (64-bit, prefetchable) [virtual] [size=16K] Region 3: Memory at 281a20000 (64-bit, prefetchable) [virtual] [size=16K] $ info mtree ... address-space: pci_bridge_pci_mem 0000000000000000-ffffffffffffffff (prio 0, i/o): pci_bridge_pci 0000000081a00000-0000000081a03fff (prio 1, i/o): igbvf-mmio 0000000081a20000-0000000081a23fff (prio 1, i/o): igbvf-msix and causes MMIO accesses to fail: Invalid write at addr 0x281A01520, size 4, region '(null)', reason: rejected Invalid read at addr 0x281A00C40, size 4, region '(null)', reason: rejected To fix this, VF BARs are now registered with pci_register_bar() which has a type parameter and pcie_sriov_vf_register_bar() is removed. Fixes: cab1398a60eb ("pcie_sriov: Reuse SR-IOV VF device instances") Signed-off-by: Damien Bergamini <damien.bergamini@eviden.com> Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250901151314.1038020-1-clement.mathieu--drif@eviden.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * hw/smbios: allow clearing the VM bit in SMBIOS table 0Daniil Tatianin2025-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful to be able to freeze a specific version of SeaBIOS to prevent guest visible changes between BIOS updates. This is currently not possible since the extension byte 2 provided by SeaBIOS does not set the VM bit, whereas QEMU sets it unconditionally. Allowing to clear it also seems useful if we want to hide the fact that the guest system is running inside a virtual machine. Signed-off-by: Daniil Tatianin <d-tatianin@yandex-team.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250724195409.43499-1-d-tatianin@yandex-team.ru> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * qapi/acpi-hest: add an interface to do generic CPER error injectionMauro Carvalho Chehab2025-10-052-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a QMP command to be used for generic ACPI APEI hardware error injection (HEST) via GHESv2, and add support for it for ARM guests. Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform independent. This is mapped at arch virt bindings, depending on the types supported by QEMU and by the BIOS. So, on ARM, this is supported via ACPI_GHES_NOTIFY_GPIO notification type. This patch was co-authored: - original ghes logic to inject a simple ARM record by Shiju Jose; - generic logic to handle block addresses by Jonathan Cameron; - generic GHESv2 error inject by Mauro Carvalho Chehab; Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Co-authored-by: Shiju Jose <shiju.jose@huawei.com> Co-authored-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <81e2118b3c8b7e5da341817f277d61251655e0db.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * arm/virt: Wire up a GED error device for ACPI / GHESMauro Carvalho Chehab2025-10-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support to ARM virtualization to allow handling generic error ACPI Event via GED & error source device. It is aligned with Linux Kernel patch: https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.huang@intel.com/ Co-authored-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <3237a76b1469d669436399495825348bf34122cd.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * acpi/generic_event_device: add an APEI error deviceMauro Carvalho Chehab2025-10-043-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a generic error device to handle generic hardware error events as specified at ACPI 6.5 specification at 18.3.2.7.2: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources using HID PNP0C33. The PNP0C33 device is used to report hardware errors to the guest via ACPI APEI Generic Hardware Error Source (GHES). Co-authored-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Co-authored-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <2790f664c849d53de0ce3049fa8c7950c1de1f86.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * acpi/ghes: add a notifier to notify when error data is readyMauro Carvalho Chehab2025-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Some error injection notify methods are async, like GPIO notify. Add a notifier to be used when the error record is ready to be sent to the guest OS. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <edf9c6e5b80dc57e3443893bf9e1eb25cb9d266b.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * acpi/ghes: don't hard-code the number of sources for HEST tableMauro Carvalho Chehab2025-10-041-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code is actually dependent on having just one error structure with a single source, as any change there would cause migration issues. As the number of sources should be arch-dependent, as it will depend on what kind of notifications will exist, and how many errors can be reported at the same time, change the logic to be more flexible, allowing the number of sources to be defined when building the HEST table by the caller. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <1698680848c11d6f26368426f1657e14faaf55c4.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| * acpi/ghes: Use HEST table offsets when preparing GHES recordsMauro Carvalho Chehab2025-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two pointers that are needed during error injection: 1. The start address of the CPER block to be stored; 2. The address of the read ack. It is preferable to calculate them from the HEST table. This allows checking the source ID, the size of the table and the type of the HEST error block structures. Yet, keep the old code, as this is needed for migration purposes from older QEMU versions. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <d4344e8dbe66372e1e093d968eda2e8b0527ba48.1758610789.git.mchehab+huawei@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>