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2025-10-07target/arm: Implement APPSAARichard Henderson1-1/+2
2025-10-07target/arm: Fix GPT fault type for address outside PPSRichard Henderson1-1/+1
2025-10-07target/arm: Implement SPAD, NSPAD, RLPADRichard Henderson1-2/+21
2025-10-07target/arm: Implement GPT_NonSecureOnlyRichard Henderson1-1/+9
2025-10-07target/arm: GPT_Secure is reserved without FEAT_SEL2Richard Henderson1-4/+8
2025-10-07target/arm: Add cur_space to S1TranslateRichard Henderson1-18/+19
2025-10-07target/arm: Enable FEAT_RME_GPC2 bits in gpccr_writeRichard Henderson1-0/+5
2025-10-07target/arm: Add GPCCR fields from ARM revision L.bRichard Henderson1-0/+6
2025-10-07target/arm: Add isar feature test for FEAT_RME_GPC2Richard Henderson1-0/+5
2025-10-07hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' headerPhilippe Mathieu-Daudé3-60/+0
2025-10-07hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5Frederic Konrad2-1/+80
2025-10-07hw/arm/xlnx-zynqmp: introduce helper to compute RPU numberClément Chigot1-3/+12
2025-10-07hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in headerClément Chigot2-6/+6
2025-10-07tests/functional/test_aarch64_xlnx_versal: test the versal2 machineLuc Michel1-2/+8
2025-10-07hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machineLuc Michel2-10/+76
2025-10-07docs/system/arm/xlnx-versal-virt: add a note about dumpdtbLuc Michel1-1/+7
2025-10-07docs/system/arm/xlnx-versal-virt: update supported devicesLuc Michel1-2/+5
2025-10-07hw/arm/xlnx-versal-virt: tidy upLuc Michel1-25/+0
2025-10-07hw/arm/xlnx-versal-virt: split into base/concrete classesLuc Michel1-22/+52
2025-10-07hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virtLuc Michel3-18/+25
2025-10-07hw/arm/xlnx-versal: add versal2 SoCLuc Michel2-15/+209
2025-10-07target/arm/tcg/cpu64: add the cortex-a78ae CPULuc Michel1-0/+78
2025-10-07hw/arm/xlnx-versal: add the target field in IRQ descriptorLuc Michel1-2/+39
2025-10-07hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMapLuc Michel1-2/+13
2025-10-07hw/misc/xlnx-versal-crl: add the versal2 versionLuc Michel3-0/+722
2025-10-07hw/arm/xlnx-versal: tidy upLuc Michel2-225/+7
2025-10-07hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indicesLuc Michel2-17/+17
2025-10-07hw/arm/xlnx-versal: reconnect the CRL to the other devicesLuc Michel1-1/+30
2025-10-07hw/misc/xlnx-versal-crl: refactor device reset logicLuc Michel2-79/+92
2025-10-07hw/misc/xlnx-versal-crl: split into base/concrete classesLuc Michel2-21/+58
2025-10-07hw/misc/xlnx-versal-crl: remove unnecessary include directivesLuc Michel1-4/+1
2025-10-07hw/arm/xlnx-versal: add the versal_get_num_cpu accessorLuc Michel3-3/+13
2025-10-07hw/arm/xlnx-versal: ddr: refactor creationLuc Michel3-106/+53
2025-10-07hw/arm/xlnx-versal: ocm: refactor creationLuc Michel2-8/+16
2025-10-07hw/arm/xlnx-versal: rpu: refactor creationLuc Michel3-46/+26
2025-10-07hw/arm/xlnx-versal: add support for GICv2Luc Michel1-20/+62
2025-10-07hw/arm/xlnx-versal: add support for multiple GICsLuc Michel2-4/+53
2025-10-07hw/intc/arm_gicv3: Introduce a 'first-cpu-index' propertyFrancisco Iglesias4-2/+10
2025-10-07hw/arm/xlnx-versal: instantiate the GIC ITS in the APULuc Michel1-0/+50
2025-10-07hw/arm/xlnx-versal: add the mp_affinity property to the CPU mappingLuc Michel1-0/+16
2025-10-07hw/arm/xlnx-versal: refactor CPU cluster creationLuc Michel3-170/+276
2025-10-07hw/arm/xlnx-versal-virt: virtio: refactor creationLuc Michel3-19/+41
2025-10-07hw/arm/xlnx-versal: crl: refactor creationLuc Michel2-20/+19
2025-10-07hw/arm/xlnx-versal: cfu: refactor creationLuc Michel2-155/+113
2025-10-07hw/arm/xlnx-versal: rtc: refactor creationLuc Michel3-33/+31
2025-10-07hw/arm/xlnx-versal: trng: refactor creationLuc Michel2-10/+10
2025-10-07hw/arm/xlnx-versal: bbram: refactor creationLuc Michel3-38/+33
2025-10-07hw/arm/xlnx-versal: PMC IOU SCLR: refactor creationLuc Michel2-25/+28
2025-10-07hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQsLuc Michel1-1/+62
2025-10-07hw/arm/xlnx-versal: ospi: refactor creationLuc Michel3-97/+98