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path: root/target/avr/translate.c (follow)
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* target/avr: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé2024-03-121-2/+1
* target: Use vaddr in gen_intermediate_codeAnton Johansson2024-01-291-1/+1
* accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson2023-10-041-1/+1
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-32/+32
* accel/tcg: Introduce translator_io_startRichard Henderson2023-06-051-1/+0
* tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson2023-06-051-0/+5
* target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*Richard Henderson2023-05-051-8/+8
* target/avr: Avoid use of tcg_const_i32 throughoutRichard Henderson2023-03-131-15/+15
* target/avr: Avoid use of tcg_const_i32 in SBIC, SBISRichard Henderson2023-03-131-8/+10
* target/avr: Drop tcg_temp_freeRichard Henderson2023-03-051-228/+0
* target/avr: Drop R from trans_COMRichard Henderson2023-03-051-4/+0
* target/avr: Drop DisasContext.free_skip_var0Richard Henderson2023-03-051-19/+0
* accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson2023-03-011-1/+1
* target/avr: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-6/+0
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+3
* target/avr: Disable interrupts when env->skip setRichard Henderson2022-09-011-4/+22
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-3/+4
* target/avr: Drop checks for singlestep_enabledRichard Henderson2021-10-151-15/+4
* target/avr: Fix compiler errors (-Werror=enum-conversion)Stefan Weil2021-09-161-5/+3
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-18/+0
* target/avr: Implement gdb_adjust_breakpointRichard Henderson2021-07-211-14/+0
* target/avr: Use translator_use_goto_tbRichard Henderson2021-07-091-3/+6
* target/avr: Convert to TranslatorOpsRichard Henderson2021-06-291-104/+126
* target/avr: Change ctx to DisasContext* in gen_intermediate_codeRichard Henderson2021-06-291-41/+43
* target/avr: Add DisasContextBase to DisasContextRichard Henderson2021-06-291-29/+29
* meson: targetPaolo Bonzini2020-08-211-1/+1
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
* target/avr: Add support for disassembling via option '-d in_asm'Michael Rolnik2020-07-111-0/+12
* target/avr: Initialize TCG register variablesMichael Rolnik2020-07-111-0/+29
* target/avr: Add instruction translation - CPU main translation functionMichael Rolnik2020-07-111-0/+213
* target/avr: Add instruction translation - MCU Control InstructionsMichael Rolnik2020-07-111-0/+65
* target/avr: Add instruction translation - Bit and Bit-test InstructionsMichael Rolnik2020-07-111-0/+247
* target/avr: Add instruction translation - Data Transfer InstructionsMichael Rolnik2020-07-111-0/+990
* target/avr: Add instruction translation - Branch InstructionsMichael Rolnik2020-07-111-0/+543
* target/avr: Add instruction translation - Arithmetic and Logic InstructionsMichael Rolnik2020-07-111-0/+820
* target/avr: Add instruction translation - Register definitionsMichael Rolnik2020-07-111-0/+142