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* target/loongarch: Add header file cpu-mmu.hBibo Mao2025-08-291-20/+0
| | | | | | | | New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Move definition of TCG specified function to tcg directoryBibo Mao2025-04-241-5/+0
| | | | | | | | | | Function loongarch_cpu_tlb_fill() only works in TCG mode, move its definition from header file internals.h to file tcg/tcg_loongarch.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-10-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* target/loongarch: Add static definition with function loongarch_tlb_search()Bibo Mao2025-04-241-2/+0
| | | | | | | | | | Function loongarch_tlb_search() is only referenced in file tcg/tlb_helper.c, define this function with static attribution. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250423080417.3739809-9-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* target/loongarch: fix bad shift in check_ps()Song Gao2025-03-211-1/+1
| | | | | | | | | | | | | | In expression 1ULL << tlb_ps, left shifting by more than 63 bits has undefined behavior. The shift amount, tlb_ps, is as much as 64. check "tlb_ps >=64" to fix. Resolves: Coverity CID 1593475 Fixes: d882c284a3 ("target/loongarch: check tlb_ps") Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
* target/loongarch: check tlb_psSong Gao2025-03-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | For LoongArch th min tlb_ps is 12(4KB), for TLB code, the tlb_ps may be 0,this may case UndefinedBehavior Add a check-tlb_ps fuction to check tlb_ps, to make sure the tlb_ps is avalablie. we check tlb_ps when get the tlb_ps from tlb->misc or CSR bits. 1. cpu reset set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits a default value from CSR_PRCFG2; 2. tlb instructions. some tlb instructions get the tlb_ps from tlb->misc but the value may has been initialized to 0. we need just check the tlb_ps skip the function and write a guest log. 3. csrwr instructions. to make sure CSR_PWCL.PTBASE and CSR_STLBPS.PS bits are avalable, cheke theses bits and set a default value from CSR_PRCFG2. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20250305063311.830674-3-gaosong@loongson.cn>
* target/loongarch: Add page table walker support for debugger usageMiao Hao2025-01-151-1/+3
| | | | | | | | | | | When dump memory content with gva address, software page table walker is necessary to get responding gpa address. Here page table walker is added for debugger usage. Signed-off-by: Miao Hao <haomiao23s@ict.ac.cn> Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
* accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_coreRichard Henderson2024-12-241-0/+2
| | | | | | | | | Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Declare loongarch_cpu_dump_state() locallyPhilippe Mathieu-Daudé2024-12-201-2/+0
| | | | | | | | | | loongarch_cpu_dump_state() is not used outside of cpu.c, no need to expose its prototype. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241115152053.66442-3-philmd@linaro.org>
* target/loongarch: Support QMP dump-guest-memoryBibo Mao2024-09-121-0/+2
| | | | | | | | | | | | | | Add the support needed for creating prstatus elf notes. This allows us to use QMP dump-guest-memory. Now ELF notes of LoongArch only supports general elf notes, LSX and LASX is not supported, since it is mainly used to dump guest memory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240822065245.2286214-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* target/loongarch: Fix tlb huge page loading issueXianglai Li2024-03-201-5/+0
| | | | | | | | | | | | | | | | | When we use qemu tcg simulation, the page size of bios is 4KB. When using the level 2 super huge page (page size is 1G) to create the page table, it is found that the content of the corresponding address space is abnormal, resulting in the bios can not start the operating system and graphical interface normally. The lddir and ldpte instruction emulation has a problem with the use of super huge page processing above level 2. The page size is not correctly calculated, resulting in the wrong page size of the table entry found by tlb. Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240318070332.1273939-1-lixianglai@loongson.cn>
* target/loongarch: Fix qtest test-hmp error when KVM-only buildSong Gao2024-02-011-2/+18
| | | | | | | | | The cc->sysemu_ops->get_phys_page_debug() is NULL when KVM-only build. this patch fixes it. Signed-off-by: Song Gao <gaosong@loongson.cn> Tested-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240125061401.52526-1-gaosong@loongson.cn>
* target/loongarch: Implement kvm get/set registersTianrui Zhao2024-01-111-1/+4
| | | | | | | | | | | | | Implement kvm_arch_get/set_registers interfaces, many regs can be get/set in the function, such as core regs, csr regs, fpu regs, mp state, etc. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: xianglai li <lixianglai@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Change-Id: Ia8fc48fe08b1768853f7729e77d37cdf270031e4 Message-Id: <20240105075804.1228596-5-zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
* target/loongarch: Add LASX data supportSong Gao2023-09-201-22/+0
| | | | | | Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-12-gaosong@loongson.cn>
* target/loongarch: Implement LSX fpu arith instructionsSong Gao2023-05-061-0/+1
| | | | | | | | | | | | | | | This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
* target/loongarch: Add LSX data type VRegSong Gao2023-05-061-0/+22
| | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-2-gaosong@loongson.cn>
* target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()Song Gao2022-08-051-0/+3
| | | | | | | | | | GDB LoongArch fpu use fcc register, update gdb_set_fpu() and gdb_get_fpu() to match it. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220805033523.1416837-6-gaosong@loongson.cn>
* target/loongarch: Adjust functions and structure to support user-modeSong Gao2022-07-041-0/+2
| | | | | | | | | | | Some functions and member of the structure are different with softmmu-mode So we need adjust them to support user-mode. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220624031049.1716097-12-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add gdb support.Xiaojuan Yang2022-06-061-0/+4
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-42-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add other core instructions supportXiaojuan Yang2022-06-061-0/+5
| | | | | | | | | | | | | | | | This includes: -CACOP -LDDIR -LDPTE -ERTN -DBCL -IDLE Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-29-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add constant timer supportXiaojuan Yang2022-06-061-0/+6
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-25-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add LoongArch interrupt and exception handleXiaojuan Yang2022-06-061-0/+2
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-24-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add MMU support for LoongArch CPU.Xiaojuan Yang2022-06-061-0/+9
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-23-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add basic vmstate description of CPU.Xiaojuan Yang2022-06-061-0/+2
| | | | | | | | Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-21-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add floating point comparison instruction translationSong Gao2022-06-061-0/+5
| | | | | | | | | | | This includes: - FCMP.cond.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-12-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add floating point arithmetic instruction translationSong Gao2022-06-061-0/+2
| | | | | | | | | | | | | | | | | | This includes: - F{ADD/SUB/MUL/DIV}.{S/D} - F{MADD/MSUB/NMADD/NMSUB}.{S/D} - F{MAX/MIN}.{S/D} - F{MAXA/MINA}.{S/D} - F{ABS/NEG}.{S/D} - F{SQRT/RECIP/RSQRT}.{S/D} - F{SCALEB/LOGB/COPYSIGN}.{S/D} - FCLASS.{S/D} Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-11-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/loongarch: Add core definitionSong Gao2022-06-061-0/+21
This patch adds target state header, target definitions and initialization routines. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220606124333.2060567-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>