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* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-031-8/+15
| | | | | | | | | | | | | The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Reduce tlb to a single dimensionRichard Henderson2018-07-031-4/+2
| | | | | | | | | While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-031-11/+0
| | | | | | | | There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-031-2/+4
| | | | | | | | | | | | | | There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-031-0/+1
| | | | | | | | | Rather than emit disassembly while translating, reuse the generated decoder to build a separate disassembler. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* cpu: get rid of unused cpu_init() definesIgor Mammedov2018-03-191-2/+0
| | | | | | | | | | | cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
| | | | | | | | | | | | | | | | | | it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-211-1/+0
| | | | | | | | | | | | | | | | | As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
* openrisc: cleanup cpu type name compositionIgor Mammedov2017-10-271-0/+3
| | | | | | | | | | | | use new OPENRISC_CPU_TYPE_NAME to compose CPU type name and get rid of intermediate OpenRISCCPUInfo/openrisc_cpu_register_types() which is replaced by static TypeInfo array. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-18-git-send-email-imammedo@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-211-1/+3
| | | | | | | | | | | | | In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
* openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2017-09-011-3/+1
| | | | | | | | | | it's just a wrapper, drop it and use cpu_generic_init() directly Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1503592308-93913-24-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+10
| | | | | | | | | | | | | | | | | | | | | | The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model (SUME) - Stop cpu and all units - wake on reset The linux kernel will set DME when idle. This patch implements the PMR SPR and halts the qemu cpu when there is a change to DME or SME. This means that openrisc qemu in no longer peggs a host cpu at 100%. In order for this to work we need to kick the CPU when timers are expired. Update the cpu timer to kick the cpu upon each timer event. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Remove duplicate features propertyStafford Horne2017-05-041-14/+2
| | | | | | | | | | | | The features property has stored the exact same thing as the cpucfgr spr. Remove the feature enum and property as it is not needed. In order to preserve the behavior or keeping features accross reset this patch moves cpucfgr into the non reset region of the state struct. Since the cpucfgr is read only this means we only need to sset cpucfgr once during class init. Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: implement shadow registersStafford Horne2017-05-041-2/+13
| | | | | | | | | | | | | | | | Shadow registers are part of the openrisc spec along with sr[cid], as part of the fast context switching feature. When exceptions occur, instead of having to save registers to the stack if enabled the CID will increment and a new set of registers will be available. This patch only implements shadow registers which can be used as extra scratch registers via the mfspr and mtspr if required. This is implemented in a way where it would be easy to add on the fast context switching, currently cid is hardcoded to 0. This is need for openrisc linux smp kernels to boot correctly. Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-0/+7
| | | | | | | | | | | | | | | Exception Vector Base Address Register (EVBAR) - This optional register can be used to apply an offset to the exception vector addresses. The significant bits (31-12) of the vector offset address for each exception depend on the setting of the Supervision Register (SR)'s EPH bit and the Exception Vector Base Address Register (EVBAR). Its presence is indicated by the EVBARP bit in the CPU Configuration Register (CPUCFGR). Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
* target/openrisc: Optimize for r0 being zeroRichard Henderson2017-02-141-1/+4
| | | | | | | | | The HW does not special-case r0, but the ABI specifies that r0 should contain 0. If we expose this fact to the optimizer, we can simplify a lot of the generated code. We must of course verify that r0==0, but that is trivial to do with a TB flag. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Tidy handling of delayed branchesRichard Henderson2017-02-141-7/+5
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Tidy ppc/npc implementationRichard Henderson2017-02-141-1/+1
| | | | | | | | | | | | The NPC SPR is really only supposed to be used for FPGA debugging. It contains the same contents as PC, unless one plays games. Follow the or1ksim implementation in flushing delayed branch state when it is changed. The PPC SPR need not be updated every instruction, merely when we exit the TB or attempt to read its contents. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Fix maddRichard Henderson2017-02-141-3/+0
| | | | | | | | | | Note that the specification for lf.madd.s is confused. It's the only mention of supposed FPMADDHI/FPMADDLO special registers. On the other hand, or1ksim implements a somewhat normal non-fused multiply and add. Mirror that. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson2017-02-141-2/+1
| | | | | | | Significantly simplifies the implementation of the use of MAC. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson2017-02-141-3/+10
| | | | | | This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-141-2/+13
| | | | | | | This avoids having to keep merging and extracting the flag from SR. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Put SR[OVE] in TB flagsRichard Henderson2017-02-141-2/+2
| | | | | | Removes a call at execution time for overflow exceptions. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Implement lwa, swaRichard Henderson2017-02-141-0/+3
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target/openrisc: Rename the cpu from or32 to or1kRichard Henderson2017-02-141-1/+1
| | | | | | This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net>
* qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+411
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>