summary refs log tree commit diff stats
path: root/target/riscv/cpu.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell2024-04-251-2/+2
* target/riscv: do not enable all named features by defaultDaniel Henrique Barboza2024-03-221-31/+9
* target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handlerPhilippe Mathieu-Daudé2024-03-121-1/+1
* target/riscv: move ratified/frozen exts to non-experimentalDaniel Henrique Barboza2024-03-081-13/+9
* RISC-V: Add support for ZtsoPalmer Dabbelt2024-03-081-0/+2
* target/riscv: Promote svade to a normal extensionAndrew Jones2024-03-081-7/+2
* target/riscv: Gate hardware A/D PTE bit updatingAndrew Jones2024-03-081-1/+2
* target/riscv: Reset henvcfg to zeroAndrew Jones2024-03-081-2/+1
* target/riscv: add remaining named featuresDaniel Henrique Barboza2024-03-081-7/+35
* target/riscv: add riscv,isa to named featuresDaniel Henrique Barboza2024-03-081-4/+13
* hw/core/cpu: Remove gdb_get_dynamic_xml memberAkihiko Odaki2024-02-281-14/+0
* gdbstub: Infer number of core registers from XMLAkihiko Odaki2024-02-281-1/+0
* target/riscv: Use GDBFeature for dynamic XMLAkihiko Odaki2024-02-281-2/+2
* target/riscv: add rv32i, rv32e and rv64e CPUsDaniel Henrique Barboza2024-02-091-0/+21
* target/riscv/cpu.c: add riscv_bare_cpu_init()Daniel Henrique Barboza2024-02-091-16/+29
* target/riscv: support new isa extension detection devicetree propertiesConor Dooley2024-02-091-0/+54
* target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...Conor Dooley2024-02-091-1/+9
* target/riscv: Expose Zaamo and Zalrsc extensionsRob Bradford2024-02-091-0/+5
* target/riscv: Validate misa_mxl_max only onceAkihiko Odaki2024-02-091-0/+21
* target/riscv: Move misa_mxl_max to classAkihiko Odaki2024-02-091-76/+84
* target/riscv/cpu.c: remove cpu->cfg.vlenDaniel Henrique Barboza2024-02-091-5/+3
* target/riscv: add 'vlenb' field in cpu->cfgDaniel Henrique Barboza2024-02-091-1/+3
* target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-53/+57
* target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-32/+36
* target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-32/+37
* target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza2024-02-091-5/+0
* target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-1/+37
* target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-1/+37
* target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-1/+38
* target/riscv: create finalize_features() for KVMDaniel Henrique Barboza2024-02-091-5/+11
* target/riscv: move 'elen' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-2/+42
* target/riscv: move 'vlen' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-1/+44
* target/riscv: rework 'vext_spec'Daniel Henrique Barboza2024-02-091-2/+33
* target/riscv: rework 'priv_spec'Daniel Henrique Barboza2024-02-091-1/+72
* target/riscv: move 'pmp' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-2/+36
* target/riscv: move 'mmu' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-4/+51
* target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-7/+84
* target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza2024-02-091-0/+5
* target/riscv: Add infrastructure for 'B' MISA extensionRob Bradford2024-02-091-2/+3
* target/riscv: Populate CPUClass.mmu_indexRichard Henderson2024-02-031-0/+6
* target/riscv: Ensure mideleg is set correctly on resetAlistair Francis2024-01-101-0/+8
* target/riscv: add rva22s64 cpuDaniel Henrique Barboza2024-01-101-0/+8
* target/riscv: add RVA22S64 profileDaniel Henrique Barboza2024-01-101-0/+32
* target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv: add satp_mode profile supportDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza2024-01-101-1/+6
* target/riscv/cpu.c: finalize satp_mode earlierDaniel Henrique Barboza2024-01-101-8/+8
* target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv: implement svadeDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza2024-01-101-0/+17