summary refs log tree commit diff stats
path: root/target/riscv/cpu.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'Philippe Mathieu-Daudé2024-04-261-2/+0
* target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bitVadim Shakirov2024-03-081-4/+4
* target/riscv: Use GDBFeature for dynamic XMLAkihiko Odaki2024-02-281-2/+3
* target/riscv: support new isa extension detection devicetree propertiesConor Dooley2024-02-091-0/+1
* target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG...Conor Dooley2024-02-091-0/+1
* target/riscv: Move misa_mxl_max to classAkihiko Odaki2024-02-091-2/+2
* target/riscv: change vext_get_vlmax() argumentsDaniel Henrique Barboza2024-02-091-4/+3
* target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax()Daniel Henrique Barboza2024-02-091-2/+9
* target/riscv: Implement optional CSR mcontext of debug Sdtrig extensionAlvin Chang2024-02-091-0/+1
* target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza2024-02-091-1/+0
* target/riscv: create finalize_features() for KVMDaniel Henrique Barboza2024-02-091-0/+1
* target/riscv: rework 'vext_spec'Daniel Henrique Barboza2024-02-091-0/+1
* target/riscv: rework 'priv_spec'Daniel Henrique Barboza2024-02-091-0/+3
* target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza2024-02-091-0/+1
* target/riscv/cpu_cfg.h: remove unused fieldsDaniel Henrique Barboza2024-02-091-1/+0
* target/riscv: Add infrastructure for 'B' MISA extensionRob Bradford2024-02-091-0/+1
* include/exec: Implement cpu_mmu_index genericallyRichard Henderson2024-02-031-2/+0
* target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_indexRichard Henderson2024-02-031-2/+2
* target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv: add satp_mode profile supportDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza2024-01-101-0/+1
* target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza2024-01-101-0/+2
* target/riscv: add rva22u64 profile definitionDaniel Henrique Barboza2024-01-101-0/+12
* target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza2024-01-101-0/+1
* target/riscv: Use generic cpu_list()Gavin Shan2024-01-051-2/+0
* target/riscv/cpu.h: spelling fix: separatlyMichael Tokarev2023-11-151-2/+2
* target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2023-11-071-0/+16
* target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'Philippe Mathieu-Daudé2023-11-071-0/+6
* target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'Philippe Mathieu-Daudé2023-11-071-0/+2
* target: Unify QOM stylePhilippe Mathieu-Daudé2023-11-071-2/+0
* target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza2023-11-071-0/+1
* target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza2023-11-071-0/+1
* target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal2023-11-071-0/+14
* target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal2023-11-071-0/+8
* target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal2023-11-071-0/+1
* target/riscv: deprecate capital 'Z' CPU propertiesDaniel Henrique Barboza2023-10-121-0/+1
* target/riscv: add riscv_cpu_get_name()Daniel Henrique Barboza2023-10-121-0/+1
* target/riscv/cpu: move priv spec functions to tcg-cpu.cDaniel Henrique Barboza2023-10-121-2/+0
* target/riscv/cpu.c: export isa_edata_arr[]Daniel Henrique Barboza2023-10-121-0/+7
* target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.cDaniel Henrique Barboza2023-10-121-1/+0
* target/riscv/tcg: introduce tcg_cpu_instance_init()Daniel Henrique Barboza2023-10-121-1/+0
* target/riscv/cpu.c: export set_misa()Daniel Henrique Barboza2023-10-121-0/+1
* target/riscv/kvm: do not use riscv_cpu_add_misa_properties()Daniel Henrique Barboza2023-10-121-1/+2
* target/riscv: make riscv_add_satp_mode_properties() publicDaniel Henrique Barboza2023-10-121-0/+1
* target/riscv: move riscv_cpu_add_kvm_properties() to kvm.cDaniel Henrique Barboza2023-10-121-0/+14
* target/riscv: move riscv_tcg_ops to tcg-cpu.cDaniel Henrique Barboza2023-10-121-4/+0
* target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza2023-10-121-1/+7
* target/riscv: introduce TCG AccelCPUClassDaniel Henrique Barboza2023-10-121-0/+4
* target/riscv: make CPUCFG() macro publicDaniel Henrique Barboza2023-10-121-0/+2
* accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson2023-10-031-1/+1