summary refs log tree commit diff stats
path: root/target/riscv/helper.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Add Zvksed ISA extension supportMax Chou2023-09-111-0/+4
* target/riscv: Add Zvkg ISA extension supportNazar Kazakov2023-09-111-0/+3
* target/riscv: Add Zvksh ISA extension supportLawrence Hunter2023-09-111-0/+3
* target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk2023-09-111-0/+6
* target/riscv: Add Zvkned ISA extension supportNazar Kazakov2023-09-111-0/+14
* target/riscv: Add Zvbb ISA extension supportDickon Hood2023-09-111-0/+62
* target/riscv: Add Zvbc ISA extension supportLawrence Hunter2023-09-111-0/+6
* riscv: Add support for the Zfa extensionChristoph Müllner2023-07-101-0/+19
* target/riscv: Add support for Zvfbfwma extensionWeiwei Li2023-07-101-0/+3
* target/riscv: Add support for Zvfbfmin extensionWeiwei Li2023-07-101-0/+3
* target/riscv: Add support for Zfbfmin extensionWeiwei Li2023-07-101-0/+4
* target/riscv: Handle HLV, HSV via helpersRichard Henderson2023-05-051-2/+10
* target/riscv: add support for Zcmt extensionWeiwei Li2023-05-051-0/+3
* target/riscv: implement Zicbom extensionChristoph Muellner2023-03-051-0/+2
* target/riscv: implement Zicboz extensionChristoph Muellner2023-03-051-0/+3
* RISC-V: Adding XTheadSync ISA extensionChristoph Müllner2023-02-071-0/+1
* target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson2023-01-201-1/+0
* target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson2023-01-201-0/+1
* target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei2023-01-061-0/+2
* target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu2022-09-271-5/+10
* target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li2022-04-291-0/+3
* target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li2022-04-291-0/+8
* target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li2022-04-291-0/+6
* target/riscv: rvk: add support for zbkx extensionWeiwei Li2022-04-291-0/+2
* target/riscv: rvk: add support for zbkb extensionWeiwei Li2022-04-291-0/+3
* target/riscv: optimize helper for vmv<nr>r.vWeiwei Li2022-04-221-4/+1
* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-031-1/+1
* target/riscv: add support for zfinxWeiwei Li2022-03-031-1/+1
* target/riscv: Don't save pc when exception returnLIU Zhiwei2022-01-211-2/+2
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-081-0/+3
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-081-0/+6
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-0/+5
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-201-10/+12
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-201-6/+0
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-201-22/+0
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-201-0/+7
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-201-0/+16
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-201-0/+14
* target/riscv: rvv-1.0: register gather instructionsFrank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: count population in mask instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang2021-12-201-0/+21