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path: root/target/riscv/insn_trans/trans_privileged.c.inc (follow)
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* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-4/+4
* target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li2023-06-131-1/+1
* accel/tcg: Introduce translator_io_startRichard Henderson2023-06-051-6/+2
* target/riscv: Separate priv from mmu_idxFei Wu2023-05-051-1/+1
* target/riscv: Fix itrigger when icount is usedLIU Zhiwei2023-05-051-0/+6
* target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei2023-01-061-2/+2
* target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell2022-09-131-1/+2
* target/riscv: Minimize the calls to decode_save_opcRichard Henderson2022-07-031-0/+4
* target/riscv: Sign extend pc for different XLENLIU Zhiwei2022-01-211-1/+1
* target/riscv: Don't save pc when exception returnLIU Zhiwei2022-01-211-5/+2
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-151-2/+2
* target/riscv: Remove dead code after exceptionRichard Henderson2021-10-151-5/+1
* riscv: Add semihosting supportKeith Packard2021-01-181-1/+36
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+97