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path: root/target/riscv/insn_trans/trans_rva.c.inc (follow)
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* RISC-V: Add support for ZtsoPalmer Dabbelt2024-03-081-3/+8
* target/riscv: Check 'A' and split extensions for atomic instructionsRob Bradford2024-02-091-22/+34
* target/riscv: Check for 'A' extension on all atomic instructionsRob Bradford2024-02-091-0/+11
* target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel2023-02-071-3/+7
* target/riscv: Calculate address according to XLENLIU Zhiwei2022-01-211-6/+3
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-11/+11
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-281-0/+3
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-9/+9
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-3/+11
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+224