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path: root/target/riscv/insn_trans/trans_rvd.c.inc (follow)
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* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-24/+24
* target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li2023-06-131-5/+7
* target/riscv: add support for Zcd extensionWeiwei Li2023-05-051-0/+18
* target/riscv: Drop tcg_temp_freeRichard Henderson2023-03-051-2/+0
* target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel2023-02-071-0/+2
* target/riscv: add support for zdinxWeiwei Li2022-03-031-78/+207
* target/riscv: Calculate address according to XLENLIU Zhiwei2022-01-211-17/+2
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-081-2/+2
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-281-0/+2
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-16/+16
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-3/+14
* target/riscv: check before allocating TCG tempsLIU Zhiwei2020-08-211-4/+4
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+441