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path: root/target/riscv/insn_trans/trans_rvm.c.inc (follow)
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* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-8/+8
* target/riscv: Drop tcg_temp_freeRichard Henderson2023-03-051-33/+0
* target/riscv: add support for zmmul extension v0.1Weiwei Li2022-06-101-6/+12
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-081-13/+169
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-081-13/+13
* target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-221-3/+23
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-221-5/+5
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-011-0/+127
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-011-8/+8
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-011-8/+8
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-6/+6
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-2/+10
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-0/+120