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path: root/target/riscv/insn_trans/trans_rvvk.c.inc (follow)
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* target/riscv: enable 'vstart_eq_zero' in the end of insnsIvan Klokov2024-03-221-6/+6
* target/riscv: remove 'over' brconds from vector transDaniel Henrique Barboza2024-03-221-18/+0
* target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb'Daniel Henrique Barboza2024-02-091-8/+8
* target/riscv: Replace Zvbb checking by ZvkbMax Chou2023-11-071-13/+24
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-15/+15
* target/riscv: Add Zvksed ISA extension supportMax Chou2023-09-111-0/+43
* target/riscv: Add Zvkg ISA extension supportNazar Kazakov2023-09-111-0/+30
* target/riscv: Add Zvksh ISA extension supportLawrence Hunter2023-09-111-0/+31
* target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk2023-09-111-0/+129
* target/riscv: Add Zvkned ISA extension supportNazar Kazakov2023-09-111-0/+147
* target/riscv: Add Zvbb ISA extension supportDickon Hood2023-09-111-0/+164
* target/riscv: Add Zvbc ISA extension supportLawrence Hunter2023-09-111-0/+62