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path: root/target/riscv/insn_trans/trans_rvzfh.c.inc (follow)
Commit message (Expand)AuthorAgeFilesLines
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-27/+27
* riscv: spelling fixesMichael Tokarev2023-09-081-2/+2
* target/riscv: Add support for Zfbfmin extensionWeiwei Li2023-07-101-6/+6
* target/riscv: Avoid tcg_const_*Richard Henderson2023-03-051-1/+1
* target/riscv: Drop tcg_temp_freeRichard Henderson2023-03-051-10/+0
* target/riscv: Drop temp_newRichard Henderson2023-03-051-1/+1
* target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li2023-03-011-13/+12
* target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel2023-02-071-0/+2
* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-031-95/+237
* target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich2022-02-161-2/+2
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-201-8/+14
* target/riscv: zfh: half-precision floating-point classifyKito Cheng2021-12-201-0/+12
* target/riscv: zfh: half-precision floating-point compareKito Cheng2021-12-201-0/+37
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+288
* target/riscv: zfh: half-precision computationalKito Cheng2021-12-201-0/+129
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+65