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path: root/target/riscv/insn_trans/trans_xthead.c.inc (follow)
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* target/riscv: Enable xtheadsync under user modeLIU Zhiwei2024-02-091-10/+0
* target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei2024-01-101-1/+1
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-1/+1
* target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li2023-06-131-1/+1
* target/riscv: Separate priv from mmu_idxFei Wu2023-05-051-13/+1
* target/riscv: Drop tcg_temp_freeRichard Henderson2023-03-051-23/+1
* RISC-V: XTheadMemPair: Remove register restrictions for store-pairChristoph Müllner2023-03-011-4/+0
* RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner2023-02-071-0/+45
* RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner2023-02-071-0/+108
* RISC-V: Adding T-Head MemIdx extensionChristoph Müllner2023-02-071-0/+387
* RISC-V: Adding T-Head MemPair extensionChristoph Müllner2023-02-071-0/+92
* RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner2023-02-071-0/+83
* RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner2023-02-071-0/+35
* RISC-V: Adding XTheadBs ISA extensionChristoph Müllner2023-02-071-0/+15
* RISC-V: Adding XTheadBb ISA extensionChristoph Müllner2023-02-071-0/+124
* RISC-V: Adding XTheadBa ISA extensionChristoph Müllner2023-02-071-0/+39
* RISC-V: Adding XTheadSync ISA extensionChristoph Müllner2023-02-071-0/+85
* RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner2023-02-071-0/+81