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path: root/target/riscv/pmp.c (follow)
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* target/riscv: pmp: Ignore writes when RW=01 and MML=0Ivan Klokov2024-01-101-1/+1
* target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov2024-01-101-14/+12
* target/riscv: pmp: Ignore writes when RW=01Mayuresh Chitale2023-11-071-0/+5
* target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale2023-11-071-0/+10
* Add epmp to extensions list and rename it to smepmpHimanshu Chauhan2023-11-071-6/+6
* target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changesLeon Schuermann2023-09-111-0/+4
* target/riscv: Smepmp: Return error when access permission not allowed in PMPHimanshu Chauhan2023-06-131-8/+2
* target/riscv: Deny access if access is partially inside the PMP entryWeiwei Li2023-06-131-2/+2
* target/riscv: Separate pmp_update_rule() in pmpcfg_csr_writeWeiwei Li2023-06-131-14/+2
* target/riscv: Flush TLB only when pmpcfg/pmpaddr really changesWeiwei Li2023-06-131-10/+18
* target/riscv: Flush TLB when pmpaddr is updatedWeiwei Li2023-06-131-0/+1
* target/riscv: Update the next rule addr in pmpaddr_csr_write()Weiwei Li2023-06-131-3/+7
* target/riscv: Flush TLB when MMWP or MML bits are changedWeiwei Li2023-06-131-0/+3
* target/riscv: Remove unused paramters in pmp_hart_has_privs_default()Weiwei Li2023-06-131-6/+3
* target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabledWeiwei Li2023-06-131-24/+26
* target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li2023-06-131-19/+13
* target/riscv: Make the short cut really work in pmp_hart_has_privsWeiwei Li2023-06-131-0/+1
* target/riscv: Update pmp_get_tlb_size()Weiwei Li2023-06-131-15/+54
* target/riscv: Fix lines with over 80 charactersWeiwei Li2023-05-051-2/+4
* target/riscv: Fix format for commentsWeiwei Li2023-05-051-19/+22
* target/riscv: Fix format for indentationWeiwei Li2023-05-051-9/+10
* target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza2023-03-011-1/+1
* target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza2023-03-011-1/+1
* target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza2023-03-011-2/+2
* target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan2023-02-231-3/+6
* target/riscv: Fix PMP propagation for tlbLIU Zhiwei2023-01-061-60/+30
* target/riscv: pmp: Fixup TLB size calculationAlistair Francis2022-10-141-0/+12
* target/riscv/pmp: guard against PMP ranges with a negative sizeNicolas Pitre2022-07-031-0/+3
* target/riscv/pmp: fix NAPOT range computation overflowNicolas Pitre2022-04-221-11/+3
* target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2022-01-211-8/+4
* target/riscv: pmp: Fix some typosBin Meng2021-07-151-5/+5
* target/riscv/pmp: Add assert for ePMP operationsAlistair Francis2021-06-081-0/+4
* target/riscv/pmp: Remove outdated commentAlistair Francis2021-05-111-4/+0
* target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying2021-05-111-8/+146
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-111-0/+34
* target/riscv: Fix the PMP is locked check when using TORAlistair Francis2021-05-111-10/+16
* target/riscv: flush TLB pages if PMP permission has been changedJim Shu2021-03-221-0/+4
* target/riscv: propagate PMP permission to TLB pageJim Shu2021-03-221-21/+59
* target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-161-2/+2
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-031-11/+18
* target/riscv: Change the TLB page size depends on PMP entries.Zong Li2020-08-211-0/+52
* riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying2020-08-211-3/+2
* target/riscv: Fix pmp NA4 implementationAlexandre Mergnat2020-07-131-1/+1
* target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis2020-06-191-5/+9
* target/riscv: PMP violation due to wrong size parameterDayeol Lee2019-10-281-1/+12
* target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé2019-09-171-21/+10
* target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé2019-09-171-4/+0
* RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary2019-06-231-4/+5
* RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary2019-06-231-3/+3
* target/riscv: Fix PMP range boundary address bugDayeol Lee2019-06-231-1/+1