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path: root/target/riscv/pmp.h (follow)
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* target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov2024-01-101-4/+4
* target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale2023-11-071-0/+2
* target/riscv: Change the return type of pmp_hart_has_privs() to boolWeiwei Li2023-06-131-4/+4
* target/riscv: Update pmp_get_tlb_size()Weiwei Li2023-06-131-2/+1
* target/riscv: Fix format for indentationWeiwei Li2023-05-051-4/+5
* target/riscv: Fix PMP propagation for tlbLIU Zhiwei2023-01-061-3/+3
* target/riscv: rvk: add CSR support for ZkrWeiwei Li2022-04-291-3/+5
* target: Include missing 'cpu.h'Philippe Mathieu-Daudé2022-03-061-0/+2
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-111-0/+14
* target/riscv: propagate PMP permission to TLB pageJim Shu2021-03-221-1/+3
* target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-161-0/+1
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-031-0/+2
* target/riscv: Change the TLB page size depends on PMP entries.Zong Li2020-08-211-0/+2
* RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary2019-06-231-1/+1
* Clean up ill-advised or unusual header guardsMarkus Armbruster2019-05-131-2/+2
* RISC-V Physical Memory ProtectionMichael Clark2018-03-071-0/+64