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path: root/target/riscv/pmu.c (follow)
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* target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford2023-11-071-7/+8
* target/riscv: Use existing PMU counter mask in FDT generationRob Bradford2023-11-071-5/+1
* target/riscv: Propagate error from PMU setupRob Bradford2023-11-071-10/+9
* target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé2023-08-311-0/+1
* target/riscv: Fix lines with over 80 charactersWeiwei Li2023-05-051-1/+2
* target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li2023-05-051-2/+2
* target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley2023-05-051-1/+1
* target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li2023-05-051-3/+3
* target/riscv: Simplify getting RISCVCPU pointer from envWeiwei Li2023-05-051-4/+4
* hw/riscv: virt: Add PMU DT node to the device treeAtish Patra2022-09-071-0/+57
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-071-2/+366
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-031-0/+32