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path: root/target/riscv/tcg/tcg-cpu.c (follow)
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* target/riscv: rvv: Remove the dependency of Zvfbfmin to ZfbfminMax Chou2024-03-221-5/+0
* target/riscv: do not enable all named features by defaultDaniel Henrique Barboza2024-03-221-3/+11
* target/riscv: Promote svade to a normal extensionAndrew Jones2024-03-081-0/+6
* target/riscv: Gate hardware A/D PTE bit updatingAndrew Jones2024-03-081-10/+5
* target/riscv: add remaining named featuresDaniel Henrique Barboza2024-03-081-0/+2
* target/riscv: add riscv,isa to named featuresDaniel Henrique Barboza2024-03-081-10/+6
* target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()Daniel Henrique Barboza2024-03-081-0/+1
* target/riscv: Validate misa_mxl_max only onceAkihiko Odaki2024-02-091-23/+0
* target/riscv: Move misa_mxl_max to classAkihiko Odaki2024-02-091-6/+6
* target/riscv: Remove misa_mxl validationAkihiko Odaki2024-02-091-12/+3
* target/riscv/cpu.c: remove cpu->cfg.vlenDaniel Henrique Barboza2024-02-091-1/+3
* target/riscv: remove riscv_cpu_options[]Daniel Henrique Barboza2024-02-091-4/+0
* target/riscv: move 'elen' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-5/+0
* target/riscv: move 'vlen' to riscv_cpu_properties[]Daniel Henrique Barboza2024-02-091-5/+0
* target/riscv: rework 'vext_spec'Daniel Henrique Barboza2024-02-091-15/+0
* target/riscv: rework 'priv_spec'Daniel Henrique Barboza2024-02-091-29/+0
* target/riscv: make riscv_cpu_is_vendor() publicDaniel Henrique Barboza2024-02-091-5/+0
* target/riscv: Add step to validate 'B' extensionRob Bradford2024-02-091-0/+33
* target/riscv: Add infrastructure for 'B' MISA extensionRob Bradford2024-02-091-0/+1
* include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson2024-01-291-1/+1
* target/riscv: Rename tcg_cpu_FOO() to include 'riscv'Philippe Mathieu-Daudé2024-01-191-14/+14
* target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza2024-01-101-1/+13
* target/riscv: add satp_mode profile supportDaniel Henrique Barboza2024-01-101-0/+40
* target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza2024-01-101-0/+31
* target/riscv: implement svadeDaniel Henrique Barboza2024-01-101-0/+5
* target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza2024-01-101-0/+9
* target/riscv/tcg: validate profiles during finalizeDaniel Henrique Barboza2024-01-101-0/+69
* target/riscv/tcg: honor user choice for G MISA bitsDaniel Henrique Barboza2024-01-101-25/+48
* target/riscv/tcg: add hash table insert helpersDaniel Henrique Barboza2024-01-101-12/+16
* target/riscv/tcg: handle profile MISA bitsDaniel Henrique Barboza2024-01-101-0/+21
* target/riscv/tcg: add riscv_cpu_write_misa_bit()Daniel Henrique Barboza2024-01-101-14/+18
* target/riscv/tcg: add MISA user options hashDaniel Henrique Barboza2024-01-101-1/+14
* target/riscv/tcg: add user flag for profile supportDaniel Henrique Barboza2024-01-101-0/+80
* target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza2024-01-101-0/+26
* target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza2024-01-101-0/+32
* target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza2024-01-101-4/+9
* target/riscv: Add support for Zacas extensionWeiwei Li2024-01-101-0/+5
* target/riscv: don't verify ISA compatibility for zicntr and zihpmClément Chigot2023-11-221-0/+9
* target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford2023-11-071-2/+2
* target/riscv: Propagate error from PMU setupRob Bradford2023-11-071-1/+7
* target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou2023-11-071-0/+17
* target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou2023-11-071-0/+20
* target/riscv: Add cfg property for Zvkb extensionMax Chou2023-11-071-3/+3
* target/riscv: Add cfg property for Zvkt extensionMax Chou2023-11-071-0/+5
* target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza2023-11-071-0/+13
* target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza2023-11-071-0/+8
* Add epmp to extensions list and rename it to smepmpHimanshu Chauhan2023-11-071-2/+2
* target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza2023-11-071-1/+6
* target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza2023-11-071-28/+35
* target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal2023-11-071-1/+6