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path: root/target/riscv/translate.c (follow)
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* target/riscv: Use insn_start from DisasContextBaseRichard Henderson2024-04-091-6/+5
* target/riscv: enable 'vstart_eq_zero' in the end of insnsIvan Klokov2024-03-221-0/+6
* RISC-V: Add support for ZtsoPalmer Dabbelt2024-03-081-0/+3
* target/riscv: Move misa_mxl_max to classAkihiko Odaki2024-02-091-1/+2
* target: Use vaddr in gen_intermediate_codeAnton Johansson2024-01-291-1/+1
* target/riscv: Add support for Zacas extensionWeiwei Li2024-01-101-0/+1
* accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson2023-10-041-3/+3
* tcg: Rename cpu_env to tcg_envRichard Henderson2023-10-031-25/+25
* target/riscv: Add Zvbc ISA extension supportLawrence Hunter2023-09-111-0/+1
* riscv: Add support for the Zfa extensionChristoph Müllner2023-07-101-0/+1
* target/riscv: Add support for Zfbfmin extensionWeiwei Li2023-07-101-0/+1
* target/riscv: Add additional xlen for address when MPRV=1Weiwei Li2023-07-101-1/+12
* target/riscv: Factor out extension tests to cpu_cfg.hChristoph Müllner2023-07-101-25/+2
* target/riscv: Remove pc_succ_insn from DisasContextWeiwei Li2023-06-131-6/+1
* target/riscv: Enable PC-relative translationWeiwei Li2023-06-131-7/+40
* target/riscv: Use true diff for gen_pc_plus_diffWeiwei Li2023-06-131-7/+6
* target/riscv: Change gen_set_pc_imm to gen_update_pcWeiwei Li2023-06-131-5/+5
* target/riscv: Change gen_goto_tb to work on displacementsWeiwei Li2023-06-131-3/+5
* target/riscv: Introduce cur_insn_len into DisasContextWeiwei Li2023-06-131-1/+3
* target/riscv: Fix target address to update badaddrWeiwei Li2023-06-131-11/+10
* target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li2023-06-131-2/+3
* accel/tcg: Introduce translator_io_startRichard Henderson2023-06-051-2/+0
* tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson2023-06-051-0/+4
* target/riscv: Handle HLV, HSV via helpersRichard Henderson2023-05-051-2/+0
* target/riscv: Separate priv from mmu_idxFei Wu2023-05-051-0/+2
* target/riscv: Add a tb flags field for vstartLIU Zhiwei2023-05-051-2/+2
* target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson2023-05-051-22/+10
* target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei2023-05-051-18/+14
* target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei2023-05-051-9/+1
* target/riscv: Fix format for commentsWeiwei Li2023-05-051-8/+12
* target/riscv: Fix format for indentationWeiwei Li2023-05-051-2/+2
* target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li2023-05-051-1/+1
* target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei2023-05-051-2/+2
* target/riscv: add support for Zcmp extensionWeiwei Li2023-05-051-0/+5
* target/riscv: add support for Zcb extensionWeiwei Li2023-05-051-0/+2
* target/riscv: add support for Zca extensionWeiwei Li2023-05-051-2/+6
* Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell2023-03-071-0/+1
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| * target/riscv: implement Zicboz extensionChristoph Muellner2023-03-051-0/+1
* | target/riscv: Avoid tcg_const_*Richard Henderson2023-03-051-2/+2
* | target/riscv: Drop tcg_temp_freeRichard Henderson2023-03-051-7/+0
* | target/riscv: Drop temp_newRichard Henderson2023-03-051-24/+6
* | target/riscv: Drop ftemp_newRichard Henderson2023-03-051-20/+4
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* Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell2023-03-031-1/+2
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| * target/riscv: Add support for Zicond extensionWeiwei Li2023-03-011-0/+1
| * target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song2023-03-011-1/+1
* | accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson2023-03-011-1/+1
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* target/riscv: fix for virtual instr exceptionDeepak Gupta2023-02-071-0/+1
* RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner2023-02-071-3/+3
* RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner2023-02-071-1/+2
* RISC-V: Adding T-Head MemIdx extensionChristoph Müllner2023-02-071-1/+20