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* target/sparc: Relax decode of rs2_or_imm for v7Richard Henderson2025-09-231-19/+37
| | | | | | | | For v7, bits [12:5] are ignored for !imm. For v8, those same bits are reserved, but are not trapped. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Loosen decode of RDTBR for v7Richard Henderson2025-09-231-1/+1
| | | | | | | | | For v7, bits [18:0] are ignored. For v8, bits [18:14] are reserved and bits [13:0] are ignored. Fixes: e8325dc02d0 ("target/sparc: Move RDTBR, FLUSHW to decodetree") Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Loosen decode of RDWIM for v7Richard Henderson2025-09-231-19/+21
| | | | | | | | | For v7, bits [18:0] are ignored. For v8, bits [18:14] are reserved and bits [13:0] are ignored. Fixes: 5d617bfba07 ("target/sparc: Move RDWIM, RDPR to decodetree") Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Loosen decode of RDPSR for v7Richard Henderson2025-09-231-7/+9
| | | | | | | | | For v7, bits [18:0] are ignored. For v8, bits [18:14] are reserved and bits [13:0] are ignored. Fixes: 668bb9b755e ("target/sparc: Move RDPSR, RDHPR to decodetree") Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Loosen decode of RDY for v7Richard Henderson2025-09-232-14/+12
| | | | | | | | | | Bits [18:0] are not decoded with v7, and for v8 unused values of rs1 simply produce undefined results. Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* target/sparc: Loosen decode of STBAR for v8Richard Henderson2025-09-232-2/+16
| | | | | | | | | | | | | | Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 13 and bits 12-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). Fixes: af25071c1d ("target/sparc: Move RDASR, STBAR, MEMBAR to decodetree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3097 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* target/sparc: Allow TRANS macro with no extra argumentsRichard Henderson2025-09-231-1/+1
| | | | | | | Use ## to drop the preceding comma if __VA_ARGS__ is empty. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: limit cpu_check_irqs to system emulationPaolo Bonzini2025-09-172-0/+4
| | | | | | | | | It is not used by user-mode emulation and is the only caller of cpu_interrupt() in qemu-sparc* binaries. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wideIgor Mammedov2025-08-292-3/+3
| | | | | | | | | | | | | | | | The helpers form load-acquire/store-release pair and ensure that appropriate barriers are in place in case checks happen outside of BQL. Use them to replace open-coded checkers/setters across the code, to make sure that barriers are not missed. Helpers also make code a bit more readable. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com> Link: https://lore.kernel.org/r/20250821155603.2422553-1-imammedo@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* gdbstub: add the GDB register XML files for sparc64.Rot1272025-07-141-0/+1
| | | | | | | Signed-off-by: Rot127 <unisono@quyllur.org> Message-ID: <20250711155141.62916-2-unisono@quyllur.org> [AJB: clean up commit msg] Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
* Merge tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2025-05-281-0/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW linux-user: implement pgid field of /proc/self/stat target/sh4: Use MO_ALIGN for system UNALIGN() target/microblaze: Use TARGET_LONG_BITS == 32 for system mode accel/tcg: Add TCGCPUOps.pointer_wrap target/*: Populate TCGCPUOps.pointer_wrap # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmg2xZAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/VmAgAu5PHIARUuNqneUPQ # 2JxqpZHGVbaXE0ACi9cslpfThFM/I4OXmK21ZWb1dHB3qasNiKU8cdImXSUVH3dj # DLsr/tliReerZGUoHEtFsYd+VOtqb3wcrvXxnzG/xB761uZjFCnqwy4MrXMfSXVh # 6w+eysWOblYHQb9rAZho4nyw6BgjYAX2vfMFxLJBcDP/fjILFB7xoXHEyqKWMmE1 # 0enA0KUotyLOCRXVEXSsfPDYD8szXfMkII3YcGnscthm5j58oc3skVdKFGVjNkNb # /aFpyvoU7Vp3JpxkYEIWLQrRM75VSb1KzJwMipHgYy3GoV++BrY10T0jyEPrx0iq # RFzK4A== # =XQzq # -----END PGP SIGNATURE----- # gpg: Signature made Wed 28 May 2025 04:13:04 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250528' of https://gitlab.com/rth7680/qemu: (28 commits) accel/tcg: Assert TCGCPUOps.pointer_wrap is set target/sparc: Fill in TCGCPUOps.pointer_wrap target/s390x: Fill in TCGCPUOps.pointer_wrap target/riscv: Fill in TCGCPUOps.pointer_wrap target/ppc: Fill in TCGCPUOps.pointer_wrap target/mips: Fill in TCGCPUOps.pointer_wrap target/loongarch: Fill in TCGCPUOps.pointer_wrap target/i386: Fill in TCGCPUOps.pointer_wrap target/arm: Fill in TCGCPUOps.pointer_wrap target: Use cpu_pointer_wrap_uint32 for 32-bit targets target: Use cpu_pointer_wrap_notreached for strict align targets accel/tcg: Add TCGCPUOps.pointer_wrap target/sh4: Use MO_ALIGN for system UNALIGN() tcg: Drop TCGContext.page_{mask,bits} tcg: Drop TCGContext.tlb_dyn_max_bits target/microblaze: Simplify compute_ldst_addr_type{a,b} target/microblaze: Drop DisasContext.r0 target/microblaze: Use TARGET_LONG_BITS == 32 for system mode target/microblaze: Fix printf format in mmu_translate target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/sparc: Fill in TCGCPUOps.pointer_wrapRichard Henderson2025-05-281-0/+13
| | | | | | | | | | | | | | | | Check address masking state for sparc64. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | target/sparc: don't set FSR_NVA when comparing unordered floatsClément Chigot2025-05-271-1/+0
|/ | | | | | | | | | | | | | | | FSR_NVA should be set when one of the operands is a signaling NaN or when using FCMPEx instructions. But those cases are already handled within check_ieee_exception or floatxx_compare functions. Otherwise, it should be left untouched. FTR, this was detected by inf-compare-[5678] tests within gcc testsuites. Signed-off-by: Clément Chigot <chigot@adacore.com> Message-Id: <20250425093513.863289-1-chigot@adacore.com> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson2025-04-301-1/+2
| | | | | | | Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson2025-04-301-7/+10
| | | | | | | | | | | Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.hRichard Henderson2025-04-301-3/+0
| | | | | | | | For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* accel/tcg: Introduce TCGCPUOps.cpu_exec_resetRichard Henderson2025-04-301-0/+1
| | | | | | | | | Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé2025-04-307-7/+0
| | | | | | | | | | | | | "exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
* target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_intRichard Henderson2025-04-281-2/+1
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* qom: Constify TypeInfo::class_dataPhilippe Mathieu-Daudé2025-04-251-1/+1
| | | | | | | | All callers now correctly expect a const class data. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-5-philmd@linaro.org>
* qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé2025-04-251-2/+2
| | | | | | | | | | Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
* target/sparc: Register CPUClass:list_cpusPhilippe Mathieu-Daudé2025-04-252-4/+2
| | | | | | | | | | | Register sparc_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20250324185837.46506-5-philmd@linaro.org>
* tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported fieldPhilippe Mathieu-Daudé2025-04-231-0/+1
| | | | | | | | | | | | | Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250405161320.76854-17-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove the TCG_GUEST_DEFAULT_MO definition globallyPhilippe Mathieu-Daudé2025-04-232-24/+22
| | | | | | | | | | | By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Define guest_default_memory_order in TCGCPUOpsPhilippe Mathieu-Daudé2025-04-231-0/+2
| | | | | | | | | | | Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Restrict 'cpu_ldst.h' to accel/tcg/Philippe Mathieu-Daudé2025-04-232-2/+2
| | | | | | | | | | | | Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'Philippe Mathieu-Daudé2025-04-232-1/+2
| | | | | | | | | To avoid including the huge "cpu.h" for a simple definition, move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec/cpu-all: remove this headerPierrick Bouvier2025-04-231-2/+0
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-16-pierrick.bouvier@linaro.org>
* exec/cpu-all: transfer exec/cpu-common include to cpu.h headersPierrick Bouvier2025-04-231-0/+1
| | | | | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-15-pierrick.bouvier@linaro.org>
* exec/cpu-all: remove exec/target_page includePierrick Bouvier2025-04-233-0/+3
| | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec/cpu-all: remove exec/cpu-interrupt includePierrick Bouvier2025-04-231-0/+1
| | | | | | | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-8-pierrick.bouvier@linaro.org>
* exec/cpu-all: remove system/memory includePierrick Bouvier2025-04-232-0/+2
| | | | | | | | | | | We include this header where needed. When includes set already have ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the include. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-5-pierrick.bouvier@linaro.org>
* target/sparc: Restrict SoftMMU mmu_index() to TCGPhilippe Mathieu-Daudé2025-04-231-1/+1
| | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250401080938.32278-21-philmd@linaro.org>
* exec/cpu-all: extract tlb flags defines to exec/tlb-flags.hPierrick Bouvier2025-04-231-0/+1
| | | | | | | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250320223002.2915728-3-pierrick.bouvier@linaro.org>
* include/exec: Split out accel/tcg/cpu-mmu-index.hRichard Henderson2025-04-232-0/+2
| | | | | | | | | | | | | The implementation of cpu_mmu_index was split between cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the plumbing common to user and system mode. Using MMU_USER_IDX requires the cpu.h for a specific target, and so is restricted to when we're compiling per-target. Include the new header only where needed. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/sparc: Log unimplemented ASI load/store accessesPhilippe Mathieu-Daudé2025-03-311-0/+6
| | | | | | | | | When the cache-controller feature is not implemented, log potential ASI access as unimplemented. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Clément Chigot <chigot@adacore.com> Message-Id: <20250325123927.74939-4-philmd@linaro.org>
* hw/core/cpu: Use size_t for memory_rw_debug len argumentRichard Henderson2025-03-312-2/+2
| | | | | | | | | | Match the prototype of cpu_memory_rw_debug(). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250325224403.4011975-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
* target/sparc: Move has_work() from CPUClass to SysemuCPUOpsPhilippe Mathieu-Daudé2025-03-091-1/+3
| | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250125170125.32855-22-philmd@linaro.org>
* exec: Declare tlb_flush*() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-081-0/+1
| | | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* exec: Declare tlb_set_page_full() in 'exec/cputlb.h'Philippe Mathieu-Daudé2025-03-081-1/+1
| | | | | | | | | Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241114011310.3615-16-philmd@linaro.org>
* Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2025-03-072-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic CPUs / accelerators patch queue - Merge "qemu/clang-tsa.h" within "qemu/compiler.h" - Various cleanups around accelerators initialization code (better user/system split) - Various trivial cleanups in accel/tcg/, Guard few TCG calls with tcg_enabled() - Explicit disassemble_info endianness - Improve dual-endianness support for MicroBlaze # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfJw08ACgkQ4+MsLN6t # wN70whAAtfcdWtqseFfb6fvDtjflgxN51Ui0iaOECXUA18USKriGy34eBcMYMiM2 # +eKgU7+jI6JGE4+burcgWUsPpFFF951/A8+lyIbFgO5yToTDmC+qNe4XfmMAIyXq # uf9Obr2c0Xk9luh4odb+jPAQodw/7G1fKgcCVIJNDCl/xEcPhS9eNpTaHwcVnkWI # K6KrxWXOsqG6+evJBPWYoXtOOyt0+JcwAsJoGhprwtGm3P9+jSVXsgeGsJVyZcna # f32JtjWL754O8XeMkOn4x6rt58VrCIMKI9xT7keDyuhTCq0Zki9RO2nMU2dSw5mN # AfL9hxqUy0Nijnyslg3ugujDfTePsNyLdwwH7n0mnoD72ELi6WnhDsmOThuEB3Rd # 4/kdwTJfA/rlWk/GF1tbKW7AvQZokRARtzmL3V0HmGJu57lX+2JuszEdYBkqDEP7 # GH1I10B2yANUm+C9y3X8qWOU7Ws433ebJeJoZuyfnbZ9Me+UfRmql/oS+V8ata2i # fArEItpldUFrWRyYLkTbXrh2dgyV9yJTEir/lzOzeAZZzyabTbjf2z9qnh976GGO # 1QnDy5QA4f54kDBUZe7JK26TZsHPch7cgqXW6f8tRlJF7A9hxGK8d2TUV/lC3/vx # LUOlWNu03PhiruYmZEcWOsY3Jt9jRCF6lIryrnaJsqnVOVmMUMM= # =3TRh # -----END PGP SIGNATURE----- # gpg: Signature made Thu 06 Mar 2025 23:46:23 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'accel-cpus-20250306' of https://github.com/philmd/qemu: (54 commits) include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition system: Open-code qemu_init_arch_modules() using target_name() target/i386: Mark WHPX APIC region as little-endian target/alpha: Do not mix exception flags and FPCR bits target/riscv: Convert misa_mxl_max using GLib macros target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL target/xtensa: Finalize config in xtensa_register_core() target/sparc: Constify SPARCCPUClass::cpu_def target/i386: Constify X86CPUModel uses disas: Remove target_words_bigendian() call in initialize_debug_target() target/xtensa: Set disassemble_info::endian value in disas_set_info() target/sh4: Set disassemble_info::endian value in disas_set_info() target/riscv: Set disassemble_info::endian value in disas_set_info() target/ppc: Set disassemble_info::endian value in disas_set_info() target/mips: Set disassemble_info::endian value in disas_set_info() target/microblaze: Set disassemble_info::endian value in disas_set_info target/arm: Set disassemble_info::endian value in disas_set_info() target: Set disassemble_info::endian value for big-endian targets target: Set disassemble_info::endian value for little-endian targets target/mips: Fix possible MSA int overflow ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| * target/sparc: Constify SPARCCPUClass::cpu_defPhilippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210133134.90879-3-philmd@linaro.org>
| * target: Set disassemble_info::endian value for big-endian targetsPhilippe Mathieu-Daudé2025-03-061-0/+1
| | | | | | | | | | | | | | | | | | | | Have the CPUClass::disas_set_info() callback set the disassemble_info::endian field for big-endian targets. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250210212931.62401-3-philmd@linaro.org>
| * accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé2025-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-11-philmd@linaro.org>
* | qdev: Improve a few more PropertyInfo @description membersMarkus Armbruster2025-03-061-0/+1
| | | | | | | | | | | | Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250227085601.4140852-7-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
* | qdev: Rename PropertyInfo member @name to @typeMarkus Armbruster2025-03-061-1/+1
|/ | | | | | | | | | | PropertyInfo member @name becomes ObjectProperty member @type, while Property member @name becomes ObjectProperty member @name. Rename the former. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20250227085601.4140852-4-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [One missed instance of @type fixed]
* target/sparc: fake UltraSPARC T1 PCR and PIC registersArtyom Tarasenko2025-02-182-1/+25
| | | | | | | | | | | | | | | | Fake access to PCR Performance Control Register and PIC Performance Instrumentation Counter. Ignore writes in privileged mode, and return 0 on reads. This allows booting Tribblix, MilaX and v9os under Niagara target. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250209211248.50383-1-atar4qemu@gmail.com>
* target/sparc: Fix gdbstub incorrectly handling registers f32-f62Mikael Szreder2025-02-181-4/+14
| | | | | | | | | | | | | | | | | | The gdbstub implementation for the Sparc architecture would incorrectly calculate the the floating point register offset. This resulted in, for example, registers f32 and f34 to point to the same value. The issue was caused by the confusion between even register numbers and even register indexes. For example, the register index of f32 is 64 and f34 is 65. Cc: qemu-stable@nongnu.org Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.") Signed-off-by: Mikael Szreder <git@miszr.win> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250214070343.11501-1-git@miszr.win>
* target/sparc: Fix register selection for all F*TOx and FxTO* instructionsMikael Szreder2025-02-181-6/+6
| | | | | | | | | | | | | | | A bug was introduced in commit 0bba7572d40d which causes the fdtox and fqtox instructions to incorrectly select the destination registers. More information and a test program can be found in issue #2802. Cc: qemu-stable@nongnu.org Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802 Signed-off-by: Mikael Szreder <git@miszr.win> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [rth: Squash patches together, since the second fixes a typo in the first.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250205090333.19626-3-git@miszr.win>
* target/*: Remove TARGET_LONG_BITS from cpu-param.hRichard Henderson2025-02-081-2/+0
| | | | | | | | | This is now handled by the configs/targets/*.mak fragment. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>