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* | | target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza2024-01-101-4/+9
* | | target/riscv: create TYPE_RISCV_VENDOR_CPUDaniel Henrique Barboza2024-01-102-9/+22
* | | target/riscv: Add support for Zacas extensionWeiwei Li2024-01-106-0/+165
* | | target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()Daniel Henrique Barboza2024-01-101-19/+21
* | | target/riscv/kvm: add RISCV_CONFIG_REG()Daniel Henrique Barboza2024-01-101-14/+11
* | | target/riscv/kvm: change timer regs size to u64Daniel Henrique Barboza2024-01-101-13/+13
* | | target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64Daniel Henrique Barboza2024-01-101-3/+8
* | | target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32Daniel Henrique Barboza2024-01-101-3/+8
* | | target/riscv/cpu.c: fix machine IDs gettersDaniel Henrique Barboza2024-01-101-6/+6
* | | target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov2024-01-102-18/+16
* | | target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei2024-01-101-1/+4
* | | target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei2024-01-101-1/+1
* | | target/riscv: The whole vector register move instructions depend on vsewMax Chou2024-01-101-2/+1
* | | target/riscv: Add vill check for whole vector register move instructionsMax Chou2024-01-101-2/+3
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* | Replace "iothread lock" with "BQL" in commentsStefan Hajnoczi2024-01-082-3/+3
* | qemu/main-loop: rename qemu_cond_wait_iothread() to qemu_cond_wait_bql()Stefan Hajnoczi2024-01-082-2/+2
* | qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARDStefan Hajnoczi2024-01-084-5/+5
* | system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi2024-01-0835-211/+211
* | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingPeter Maydell2024-01-081-7/+7
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| * | target/riscv: Fix mcycle/minstret increment behaviorXu Lu2024-01-051-7/+7
* | | target/loongarch: move translate modules to tcg/Song Gao2024-01-0624-14/+20
* | | target/loongarch/meson: move gdbstub.c to loongarch.ssSong Gao2024-01-061-1/+1
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* | target/sparc: Simplify qemu_irq_ackClément Chigot2024-01-052-2/+2
* | target: Use generic cpu_model_from_type()Gavin Shan2024-01-058-16/+8
* | target/xtensa: Use generic cpu_list()Gavin Shan2024-01-052-12/+0
* | target/tricore: Use generic cpu_list()Gavin Shan2024-01-052-26/+0
* | target/sh4: Use generic cpu_list()Gavin Shan2024-01-052-20/+0
* | target/rx: Use generic cpu_list()Gavin Shan2024-01-052-19/+0
* | target/riscv: Use generic cpu_list()Gavin Shan2024-01-052-31/+0
* | target/openrisc: Use generic cpu_list()Gavin Shan2024-01-052-45/+0
* | target/mips: Use generic cpu_list()Gavin Shan2024-01-052-13/+0
* | target/m68k: Use generic cpu_list()Gavin Shan2024-01-052-44/+0
* | target/loongarch: Use generic cpu_list()Gavin Shan2024-01-052-19/+0
* | target/hppa: Use generic cpu_list()Gavin Shan2024-01-052-27/+0
* | target/hexagon: Use generic cpu_list()Gavin Shan2024-01-052-23/+0
* | target/cris: Use generic cpu_list()Gavin Shan2024-01-052-41/+0
* | target/avr: Use generic cpu_list()Gavin Shan2024-01-052-17/+0
* | target/arm: Use generic cpu_list()Gavin Shan2024-01-052-49/+0
* | target/alpha: Use generic cpu_list()Gavin Shan2024-01-052-20/+0
* | cpu: Call object_class_dynamic_cast() once in cpu_class_by_name()Philippe Mathieu-Daudé2024-01-0512-46/+11
* | target/hppa: Remove object_class_is_abstract()Gavin Shan2024-01-051-3/+1
* | target/alpha: Remove fallback to ev67 cpu classGavin Shan2024-01-051-5/+2
* | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell2024-01-0415-197/+421
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| * | meson: rename config_allPaolo Bonzini2023-12-312-2/+2
| * | target/i386: implement CMPccXADDPaolo Bonzini2023-12-295-1/+133
| * | target/i386: introduce flags writeback mechanismPaolo Bonzini2023-12-294-12/+63
| * | target/i386: adjust decoding of J operandPaolo Bonzini2023-12-291-10/+0
| * | target/i386: move operand load and writeback out of gen_cmovcc1Paolo Bonzini2023-12-291-10/+6
| * | target/i386: prepare for implementation of STOS/SCAS in new decoderPaolo Bonzini2023-12-291-2/+7
| * | target/i386: do not use s->tmp0 for jumps on ECX ==/!= 0Paolo Bonzini2023-12-291-3/+6