summary refs log tree commit diff stats
path: root/tcg/arm/tcg-target.c.inc (follow)
Commit message (Collapse)AuthorAgeFilesLines
* include/hw/core/cpu: Introduce cpu_tlb_fastRichard Henderson2025-09-231-1/+1
| | | | | | | | Encapsulate access to cpu->neg.tlb.f[] in a function. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fix tgen_depositRichard Henderson2025-09-041-1/+2
| | | | | | | | | | | | When converting from tcg_out_deposit, the arguments were not shuffled properly. Cc: qemu-stable@nongnu.org Fixes: cf4905c03135f1181e8 ("tcg: Convert deposit to TCGOutOpDeposit") Reported-by: Michael Tokarev <mjt@tls.msk.ru> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Drop TCGContext.page_{mask,bits}Richard Henderson2025-05-281-5/+5
| | | | | | Use exec/target_page.h instead of independent variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Remove tcg_out_opRichard Henderson2025-04-281-7/+0
| | | | | | | | All integer opcodes are now converted to TCGOutOp. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}Richard Henderson2025-04-281-22/+39
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}Richard Henderson2025-04-281-17/+46
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}Richard Henderson2025-04-281-8/+8
| | | | | | | | | Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two inputs or outputs are required. This simplifies the processing of i64/i128 depending on host word size. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert st to TCGOutOpStoreRichard Henderson2025-04-281-35/+37
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert ld to TCGOutOpLoadRichard Henderson2025-04-281-62/+64
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Formalize tcg_out_goto_ptrRichard Henderson2025-04-281-7/+5
| | | | | | | | | Split these functions out from tcg_out_op. Define outop_goto_ptr generically. Call tcg_out_goto_ptr from tcg_reg_alloc_op. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Formalize tcg_out_brRichard Henderson2025-04-281-3/+5
| | | | | | | | Split these functions out from tcg_out_op. Call it directly from tcg_gen_code. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Formalize tcg_out_mbRichard Henderson2025-04-281-5/+1
| | | | | | | | | | Most tcg backends already have a function for this; the rest can split one out from tcg_out_op. Call it directly from tcg_gen_code. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Implement add/sub carry opcodesRichard Henderson2025-04-281-55/+157
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Add TCGOutOp structures for add/sub carry opcodesRichard Henderson2025-04-281-0/+34
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert extract2 to TCGOutOpExtract2Richard Henderson2025-04-281-24/+14
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert deposit to TCGOutOpDepositRichard Henderson2025-04-281-13/+16
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert sextract to TCGOutOpExtractRichard Henderson2025-04-281-9/+12
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert extract to TCGOutOpExtractRichard Henderson2025-04-281-10/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert bswap64 to TCGOutOpUnaryRichard Henderson2025-04-281-0/+4
| | | | | | | | | Use TCGOutOpUnary instead of TCGOutOpBswap because the flags are not used with this opcode; they are merely present for uniformity with the smaller bswaps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert bswap32 to TCGOutOpBswapRichard Henderson2025-04-281-11/+12
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert bswap16 to TCGOutOpBswapRichard Henderson2025-04-281-21/+21
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert setcond2_i32 to TCGOutOpSetcond2Richard Henderson2025-04-281-12/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert brcond2_i32 to TCGOutOpBrcond2Richard Henderson2025-04-281-7/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Expand arguments to tcg_out_cmp2Richard Henderson2025-04-281-12/+6
| | | | | | | | Pass explicit arguments instead of arrays. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert movcond to TCGOutOpMovcondRichard Henderson2025-04-281-10/+14
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert brcond to TCGOutOpBrcondRichard Henderson2025-04-281-7/+20
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert setcond, negsetcond to TCGOutOpSetcondRichard Henderson2025-04-281-36/+81
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert mulu2 to TCGOutOpMul2Richard Henderson2025-04-281-14/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert muls2 to TCGOutOpMul2Richard Henderson2025-04-281-12/+13
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert ctpop to TCGOutOpUnaryRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert ctz to TCGOutOpBinaryRichard Henderson2025-04-281-13/+26
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert clz to TCGOutOpBinaryRichard Henderson2025-04-281-17/+30
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert rotl, rotr to TCGOutOpBinaryRichard Henderson2025-04-281-22/+22
| | | | | | | | | For aarch64, arm, loongarch64, mips, we can drop rotl. For ppc, s390x we can drop rotr. Only x86, riscv, tci have both rotl and rotr. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert sar to TCGOutOpBinaryRichard Henderson2025-04-281-7/+19
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert shr to TCGOutOpBinaryRichard Henderson2025-04-281-5/+19
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert shl to TCGOutOpBinaryRichard Henderson2025-04-281-6/+19
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert remu to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert rem to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert divu2 to TCGOutOpDivRemRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert div2 to TCGOutOpDivRemRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert divu to TCGOutOpBinaryRichard Henderson2025-04-281-13/+13
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert div to TCGOutOpBinaryRichard Henderson2025-04-281-10/+18
| | | | | | | | For TCI, we're losing type information in the interpreter. Introduce a tci-specific opcode to handle the difference. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert mulsh to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert muluh to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | | | | Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e ("tcg/riscv: Require TCG_TARGET_REG_BITS == 64"). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert mul to TCGOutOpBinaryRichard Henderson2025-04-281-11/+12
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert not to TCGOutOpUnaryRichard Henderson2025-04-281-5/+10
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert neg to TCGOutOpUnaryRichard Henderson2025-04-281-4/+10
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert sub to TCGOutOpSubtractRichard Henderson2025-04-281-11/+18
| | | | | | | | | | Create a special subclass for sub, because two backends can support "subtract from immediate". Drop all backend support for an immediate as the second operand, as we transform sub to add during optimize. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg/arm: Fix constraints for subRichard Henderson2025-04-281-7/+4
| | | | | | | | | | In 7536b82d288 we lost the rI constraint that allowed the use of RSB to perform reg = imm - reg. At the same time, drop support for reg = reg - imm, which is now transformed generically to addition, and need not be handled by the backend. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Convert nor to TCGOutOpBinaryRichard Henderson2025-04-281-0/+4
| | | | | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>