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path: root/tcg/riscv/tcg-target.c.inc (follow)
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* tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson2024-02-031-1/+2
* tcg/riscv: Use tcg_use_softmmuRichard Henderson2023-10-221-87/+90
* tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zeroRichard Henderson2023-10-221-2/+4
* tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé2023-10-071-2/+2
* tcg: Add tcg_out_tb_start backend hookRichard Henderson2023-09-161-0/+5
* tcg: pass vece to tcg_target_const_match()Jiajie Chen2023-09-151-1/+1
* tcg: spelling fixesMichael Tokarev2023-08-241-2/+2
* tcg/riscv: Implement negsetcond_*Richard Henderson2023-08-241-0/+45
* tcg: Add tlb_fast_offset to TCGContextRichard Henderson2023-06-051-3/+4
* tcg: Widen CPUTLBEntry comparators to 64-bitsRichard Henderson2023-06-051-0/+1
* tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TLRichard Henderson2023-06-051-6/+7
* tcg/riscv: Support CTZ, CLZ from ZbbRichard Henderson2023-05-251-0/+35
* tcg/riscv: Implement movcondRichard Henderson2023-05-251-1/+138
* tcg/riscv: Improve setcond expansionRichard Henderson2023-05-251-36/+114
* tcg/riscv: Support CPOP from ZbbRichard Henderson2023-05-251-0/+9
* tcg/riscv: Support REV8 from ZbbRichard Henderson2023-05-251-0/+29
* tcg/riscv: Support rotates from ZbbRichard Henderson2023-05-251-0/+34
* tcg/riscv: Use ADD.UW for guest address generationRichard Henderson2023-05-251-11/+22
* tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+ZbbRichard Henderson2023-05-251-8/+24
* tcg/riscv: Support ANDN, ORN, XNOR from ZbbRichard Henderson2023-05-251-0/+41
* tcg/riscv: Probe for Zba, Zbb, Zicond extensionsRichard Henderson2023-05-251-0/+96
* tcg: Add page_bits and page_mask to TCGContextRichard Henderson2023-05-161-2/+2
* tcg: Split INDEX_op_qemu_{ld,st}* for guest address sizeRichard Henderson2023-05-161-8/+16
* tcg/riscv: Use atom_and_align_for_opcRichard Henderson2023-05-161-5/+8
* tcg: Introduce tcg_target_has_memory_bswapRichard Henderson2023-05-161-0/+5
* tcg/riscv: Support softmmu unaligned accessesRichard Henderson2023-05-161-20/+28
* tcg/riscv: Use full load/store helpers in user-only modeRichard Henderson2023-05-161-29/+0
* tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson2023-05-161-42/+0
* tcg/riscv: Simplify constraints on qemu_ld/stRichard Henderson2023-05-111-13/+3
* tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_pathRichard Henderson2023-05-111-27/+10
* tcg/riscv: Introduce prepare_host_addrRichard Henderson2023-05-111-139/+114
* tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}Richard Henderson2023-05-051-42/+24
* tcg/riscv: Require TCG_TARGET_REG_BITS == 64Richard Henderson2023-05-051-169/+63
* tcg/riscv: Conditionalize tcg_out_exts_i32_i64Richard Henderson2023-04-231-1/+3
* tcg: Introduce tcg_out_xchgRichard Henderson2023-04-231-0/+5
* tcg: Introduce tcg_out_movextRichard Henderson2023-04-231-11/+2
* tcg: Split out tcg_out_extrl_i64_i32Richard Henderson2023-04-231-4/+6
* tcg: Split out tcg_out_extu_i32_i64Richard Henderson2023-04-231-4/+6
* tcg: Split out tcg_out_exts_i32_i64Richard Henderson2023-04-231-1/+6
* tcg: Split out tcg_out_ext32uRichard Henderson2023-04-231-1/+1
* tcg: Split out tcg_out_ext32sRichard Henderson2023-04-231-1/+1
* tcg: Split out tcg_out_ext16uRichard Henderson2023-04-231-5/+2
* tcg: Split out tcg_out_ext16sRichard Henderson2023-04-231-6/+3
* tcg: Split out tcg_out_ext8uRichard Henderson2023-04-231-5/+2
* tcg: Split out tcg_out_ext8sRichard Henderson2023-04-231-6/+3
* tcg: Introduce tcg_target_call_oarg_regRichard Henderson2023-02-041-4/+6
* tcg: Introduce tcg_out_addi_ptrRichard Henderson2023-02-041-0/+7
* tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldstRichard Henderson2023-01-201-1/+1
* tcg/riscv: Implement direct branch for goto_tbRichard Henderson2023-01-171-2/+17
* tcg/riscv: Introduce OPC_NOPRichard Henderson2023-01-171-1/+2