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/*
* QEMU emulation of an RISC-V IOMMU Platform Device
*
* Copyright (C) 2022-2023 Rivos Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci_bus.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/host-utils.h"
#include "qemu/module.h"
#include "qom/object.h"
#include "riscv-iommu.h"
#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
/* RISC-V IOMMU System Platform Device Emulation */
struct RISCVIOMMUStateSys {
SysBusDevice parent;
uint64_t addr;
uint32_t base_irq;
DeviceState *irqchip;
RISCVIOMMUState iommu;
qemu_irq irqs[RISCV_IOMMU_INTR_COUNT];
};
static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
unsigned vector)
{
RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
/* We do not support MSIs yet */
if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
return;
}
qemu_irq_pulse(s->irqs[vector]);
}
static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
{
RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev);
SysBusDevice *sysdev = SYS_BUS_DEVICE(s);
PCIBus *pci_bus;
qemu_irq irq;
qdev_realize(DEVICE(&s->iommu), NULL, errp);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
if (s->addr) {
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
}
pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL);
if (pci_bus) {
riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
}
s->iommu.notify = riscv_iommu_sysdev_notify;
/* 4 IRQs are defined starting from s->base_irq */
for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
sysbus_init_irq(sysdev, &s->irqs[i]);
irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
sysbus_connect_irq(sysdev, i, irq);
}
}
static void riscv_iommu_sys_init(Object *obj)
{
RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj);
RISCVIOMMUState *iommu = &s->iommu;
object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
qdev_alias_all_properties(DEVICE(iommu), obj);
iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
}
static Property riscv_iommu_sys_properties[] = {
DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
TYPE_DEVICE, DeviceState *),
DEFINE_PROP_END_OF_LIST(),
};
static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = riscv_iommu_sys_realize;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
device_class_set_props(dc, riscv_iommu_sys_properties);
}
static const TypeInfo riscv_iommu_sys = {
.name = TYPE_RISCV_IOMMU_SYS,
.parent = TYPE_SYS_BUS_DEVICE,
.class_init = riscv_iommu_sys_class_init,
.instance_init = riscv_iommu_sys_init,
.instance_size = sizeof(RISCVIOMMUStateSys),
};
static void riscv_iommu_register_sys(void)
{
type_register_static(&riscv_iommu_sys);
}
type_init(riscv_iommu_register_sys)
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