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| author | w4kfu <gw4kfu@gmail.com> | 2020-11-19 20:56:13 +0100 |
|---|---|---|
| committer | w4kfu <gw4kfu@gmail.com> | 2020-11-19 20:56:13 +0100 |
| commit | 4d92780a96aee4d7af3cab37547f76fde730cda9 (patch) | |
| tree | 42d68c296d05600d6e91e25f297b475395346fc8 | |
| parent | bcb5fdf783909338eaa1246796200406d90f552b (diff) | |
| download | miasm-4d92780a96aee4d7af3cab37547f76fde730cda9.tar.gz miasm-4d92780a96aee4d7af3cab37547f76fde730cda9.zip | |
[AARCH64] Fix 'extr' disassembly
| -rw-r--r-- | miasm/arch/aarch64/arch.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/miasm/arch/aarch64/arch.py b/miasm/arch/aarch64/arch.py index e32fcdd6..989e4289 100644 --- a/miasm/arch/aarch64/arch.py +++ b/miasm/arch/aarch64/arch.py @@ -1738,6 +1738,7 @@ simm7 = bs(l=7, cls=(aarch64_int64_noarg,), fname="imm", order=-1) nzcv = bs(l=4, cls=(aarch64_uint64_noarg, aarch64_arg), fname="nzcv", order=-1) uimm4 = bs(l=4, cls=(aarch64_uint64_noarg, aarch64_arg), fname="imm", order=-1) uimm5 = bs(l=5, cls=(aarch64_uint64_noarg, aarch64_arg), fname="imm", order=-1) +uimm6 = bs(l=6, cls=(aarch64_uint64_noarg, aarch64_arg), fname="imm", order=-1) uimm12 = bs(l=12, cls=(aarch64_uint64_noarg,), fname="imm", order=-1) uimm16 = bs(l=16, cls=(aarch64_uint64_noarg, aarch64_arg), fname="imm", order=-1) uimm7 = bs(l=7, cls=(aarch64_uint64_noarg,), fname="imm", order=-1) @@ -2138,7 +2139,7 @@ aarch64op("udiv", [sf, bs('0'), bs('0'), bs('11010110'), rm, bs('00001'), bs('0' # extract register p.150 -aarch64op("extr", [sf, bs('00100111'), bs(l=1, cls=(aarch64_eq,), ref="sf"), bs('0'), rm, simm6, rn, rd], [rd, rn, rm, simm6]) +aarch64op("extr", [sf, bs('00100111'), bs(l=1, cls=(aarch64_eq,), ref="sf"), bs('0'), rm, uimm6, rn, rd], [rd, rn, rm, uimm6]) # shift reg p.155 shiftr_name = {'LSL': 0b00, 'LSR': 0b01, 'ASR': 0b10, 'ROR': 0b11} |