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authorFabrice Desclaux <fabrice.desclaux@cea.fr>2015-08-23 16:47:14 +0200
committerFabrice Desclaux <fabrice.desclaux@cea.fr>2015-08-24 12:49:25 +0200
commit5f1ed09e57120dbd45d494fe5a0dc8b968f9ca41 (patch)
tree38205aca774cbd59383614325b010b532fa51b57
parent51ca7c1f27b8a6eafe07b304615d31961f7bac8d (diff)
downloadmiasm-5f1ed09e57120dbd45d494fe5a0dc8b968f9ca41.tar.gz
miasm-5f1ed09e57120dbd45d494fe5a0dc8b968f9ca41.zip
Arch/aarch64: discard writes to ZR
-rw-r--r--miasm2/arch/aarch64/sem.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py
index 9d83ccd2..f23574e6 100644
--- a/miasm2/arch/aarch64/sem.py
+++ b/miasm2/arch/aarch64/sem.py
@@ -765,6 +765,8 @@ class ir_aarch64l(ir):
                                           args[-1].args[-1][:8].zeroExtend(32))
         instr_ir, extra_ir = get_mnemo_expr(self, instr, *args)
         self.mod_pc(instr, instr_ir, extra_ir)
+        instr_ir, extra_ir = self.del_dst_zr(instr, instr_ir, extra_ir)
+
         return instr_ir, extra_ir
 
     def expr_fix_regs_for_mode(self, e):
@@ -809,6 +811,19 @@ class ir_aarch64l(ir):
                     src = src.replace_expr({self.pc: cur_offset})
                     irs[i] = m2_expr.ExprAff(dst, src)
 
+
+    def del_dst_zr(self, instr, instr_ir, extra_ir):
+        "Writes to zero register are discarded"
+        regs_to_fix = [WZR, XZR]
+        instr_ir = [expr for expr in instr_ir if expr.dst not in regs_to_fix]
+
+        for b in extra_ir:
+            for i, irs in eunmerate(b.irs):
+                b.irs[i] = [expr for expr in irs if expr.dst not in regs_to_fix]
+
+        return instr_ir, extra_ir
+
+
 class ir_aarch64b(ir_aarch64l):
 
     def __init__(self, symbol_pool=None):