about summary refs log tree commit diff stats
path: root/example/test_ida.py
diff options
context:
space:
mode:
authorserpilliere <devnull@localhost>2014-08-06 17:28:13 +0200
committerserpilliere <devnull@localhost>2014-08-06 17:28:13 +0200
commit376576de29b55f10d645bb428fab793b56cf4168 (patch)
tree6b24fe2e2e44d302a92ff74f9c1ce42a0b3b06a4 /example/test_ida.py
parent8cbb7db586badb5102d411af479e2d7ab42ce40c (diff)
downloadmiasm-376576de29b55f10d645bb428fab793b56cf4168.tar.gz
miasm-376576de29b55f10d645bb428fab793b56cf4168.zip
Add mips32 arch
Diffstat (limited to 'example/test_ida.py')
-rw-r--r--example/test_ida.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/example/test_ida.py b/example/test_ida.py
index af5727d0..405696de 100644
--- a/example/test_ida.py
+++ b/example/test_ida.py
@@ -210,6 +210,12 @@ elif processor_name == "msp430":
     # TODO ARM/thumb
     from miasm2.arch.msp430.disasm import dis_msp430 as dis_engine
     from miasm2.arch.msp430.ira import ir_a_msp430 as ira
+elif processor_name == "mipsl":
+    from miasm2.arch.mips32.disasm import dis_mips32l as dis_engine
+    from miasm2.arch.mips32.ira import ir_a_mips32 as ira
+elif processor_name == "mipsb":
+    from miasm2.arch.mips32.disasm import dis_mips32b as dis_engine
+    from miasm2.arch.mips32.ira import ir_a_mips32 as ira
 
 else:
     print repr(processor_name)