Modify irbloc destination mecanism. Rework API in consequence.

Fat patch here: some API have changed.

Each irbloc now affects a special "IRDst" register which is used to
describe the destination irbloc. It allows simple description of
architectures using delay slots. Architectures semantic and tcc/python
jitter are modified in consequence. LLVM jitter is disabled for now,
but should be patch soon.

1 files changed, 1 insertions, 0 deletions

diff --git a/miasm2/analysis/binary.py b/miasm2/analysis/binary.py
index b755aae4..c14078e3 100644
--- a/miasm2/analysis/binary.py
+++ b/miasm2/analysis/binary.py
@@ -1,6 +1,7 @@
 from miasm2.core.bin_stream import *
 import logging
 from miasm2.jitter.jitload import vm_load_pe, vm_load_elf
+from miasm2.jitter.csts import PAGE_READ
 
 log = logging.getLogger("binary")
 console_handler = logging.StreamHandler()