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authorserpilliere <serpilliere@users.noreply.github.com>2018-07-05 18:36:01 +0200
committerGitHub <noreply@github.com>2018-07-05 18:36:01 +0200
commit34aac8a90f77d461d9dee0b9cf0af3c2bff4d42f (patch)
tree359f5947d1c0b26eb9a39e2f9b8244d171348feb /miasm2/arch/arm/arch.py
parent6b6f5ab803d4f1c4d6e78c756f326e99281bc8b8 (diff)
parentdcb1d68179c3802daeeef46ef63593f59aee64e9 (diff)
downloadmiasm-34aac8a90f77d461d9dee0b9cf0af3c2bff4d42f.tar.gz
miasm-34aac8a90f77d461d9dee0b9cf0af3c2bff4d42f.zip
Merge pull request #738 from marilafo/fix_offset_branch_armtl
armtl change branch pc offset
Diffstat (limited to 'miasm2/arch/arm/arch.py')
-rw-r--r--miasm2/arch/arm/arch.py30
1 files changed, 21 insertions, 9 deletions
diff --git a/miasm2/arch/arm/arch.py b/miasm2/arch/arm/arch.py
index 1810cd6a..82664476 100644
--- a/miasm2/arch/arm/arch.py
+++ b/miasm2/arch/arm/arch.py
@@ -913,6 +913,8 @@ class arm_offs(arm_imm):
         if (1 << (self.l - 1)) & v:
             v = -((0xffffffff ^ v) + 1)
         v = self.encodeval(v)
+        if v is False:
+            return False
         self.value = (v & 0xffffffff) & self.lmask
         return True
 
@@ -1877,7 +1879,11 @@ class arm_offpc(arm_offreg):
             log.debug('cannot encode reg %r', e.args[0])
             return False
         v = int(e.args[1])
+        if v & 3:
+            return False
         v >>= 2
+        if v > self.lmask:
+            return False
         self.value = v
         return True
 
@@ -1900,8 +1906,11 @@ class arm_offspc(arm_offs):
     def encodeval(self, v):
         # Remove pipeline offset
         v -= 2 + 2
-        if v % 2 == 0:
-            return v >> 1
+        if v % 2 != 0:
+            return False
+        if v > (1 << (self.l - 1)) - 1:
+            return False
+        return v >> 1
         return False
 
 
@@ -2533,6 +2542,8 @@ class armt4_imm12(arm_imm):
         if not self.expr.is_int():
             return False
         value = int(self.expr)
+        if value >= (1 << 16):
+            return False
         self.value = value & self.lmask
         self.parent.imm12_3.value = (value >> 8) & self.parent.imm12_3.lmask
         self.parent.imm12_1.value = (value >> 11) & self.parent.imm12_1.lmask
@@ -2540,7 +2551,6 @@ class armt4_imm12(arm_imm):
 
 
 
-
 class armt2_imm16(arm_imm):
 
     def decode(self, v):
@@ -2555,6 +2565,8 @@ class armt2_imm16(arm_imm):
         if not self.expr.is_int():
             return False
         value = int(self.expr)
+        if value >= (1 << 16):
+            return False
         self.value = value & self.lmask
         self.parent.imm16_3.value = (value >> 8) & self.parent.imm16_3.lmask
         self.parent.imm16_1.value = (value >> 11) & self.parent.imm16_1.lmask
@@ -2644,8 +2656,8 @@ class armt2_imm10l(arm_imm):
         s = 0
         if v & 0x80000000:
             s = 1
-            v = (-v) & 0xffffffff
-        if v > (1 << 26):
+            v &= (1<<26) - 1
+        if v >= (1 << 26):
             return False
         i1, i2, imm10h, imm10l = (v >> 23) & 1, (v >> 22) & 1, (v >> 12) & 0x3ff, (v >> 2) & 0x3ff
         j1, j2 = i1 ^ s ^ 1, i2 ^ s ^ 1
@@ -2681,7 +2693,7 @@ class armt2_imm11l(arm_imm):
         s = 0
         if v & 0x80000000:
             s = 1
-            v = (-v) & 0xffffffff
+            v &= (1<<26) - 1
         if v >= (1 << 26):
             return False
         if v & 1:
@@ -2717,11 +2729,11 @@ class armt2_imm6_11l(arm_imm):
             return False
         v = self.expr.arg.arg - 4
         s = 0
+        if v != sign_ext(v & ((1 << 22) - 1), 21, 32):
+            return False 
         if v & 0x80000000:
             s = 1
-            v = (-v) & 0xffffffff
-        if v >= (1 << 22):
-            return False
+        v &= (1<<22) - 1
         if v & 1:
             return False
         i2, i1, imm6h, imm11l = (v >> 19) & 1, (v >> 18) & 1, (v >> 12) & 0x3f, (v >> 1) & 0x7ff