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| author | Adrien Guinet <aguinet@quarkslab.com> | 2018-07-17 16:02:22 +0200 |
|---|---|---|
| committer | Adrien Guinet <aguinet@quarkslab.com> | 2018-07-17 16:04:21 +0200 |
| commit | 5bef729fc0b33da9868ec81c7a0537905fee6b9c (patch) | |
| tree | 85ad1132aa2d1d82d60720d1faaf8c0a81b397af /miasm2/arch/arm/regs.py | |
| parent | 85904f4c55e171dec36aadc14f78113d169f6edc (diff) | |
| download | miasm-5bef729fc0b33da9868ec81c7a0537905fee6b9c.tar.gz miasm-5bef729fc0b33da9868ec81c7a0537905fee6b9c.zip | |
Support of ARM SVC in the Miasm VM
Diffstat (limited to 'miasm2/arch/arm/regs.py')
| -rw-r--r-- | miasm2/arch/arm/regs.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/miasm2/arch/arm/regs.py b/miasm2/arch/arm/regs.py index dce4cb98..e20b00bd 100644 --- a/miasm2/arch/arm/regs.py +++ b/miasm2/arch/arm/regs.py @@ -9,6 +9,7 @@ regs32_str = ["R%d" % i for i in xrange(13)] + ["SP", "LR", "PC"] regs32_expr = [ExprId(x, 32) for x in regs32_str] exception_flags = ExprId('exception_flags', 32) +interrupt_num = ExprId('interrupt_num', 32) bp_num = ExprId('bp_num', 32) @@ -84,7 +85,7 @@ all_regs_ids = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, SP, LR, PC, zf, nf, of, cf, ge0, ge1, ge2, ge3, - exception_flags, bp_num + exception_flags, interrupt_num, bp_num ] all_regs_ids_no_alias = all_regs_ids @@ -102,7 +103,7 @@ all_regs_ids_init = [R0_init, R1_init, R2_init, R3_init, R12_init, SP_init, LR_init, PC_init, zf_init, nf_init, of_init, cf_init, ge0_init, ge1_init, ge2_init, ge3_init, - ExprInt(0, 32), ExprInt(0, 32) + ExprInt(0, 32), ExprInt(0, 32), ExprInt(0, 32) ] regs_init = {} |