diff options
| author | serpilliere <serpilliere@users.noreply.github.com> | 2018-07-17 17:24:19 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-17 17:24:19 +0200 |
| commit | cf74092981e4f3fa7bed9ce182a38e570653a138 (patch) | |
| tree | 85ad1132aa2d1d82d60720d1faaf8c0a81b397af /miasm2/arch/arm/sem.py | |
| parent | 85904f4c55e171dec36aadc14f78113d169f6edc (diff) | |
| parent | 5bef729fc0b33da9868ec81c7a0537905fee6b9c (diff) | |
| download | miasm-cf74092981e4f3fa7bed9ce182a38e570653a138.tar.gz miasm-cf74092981e4f3fa7bed9ce182a38e570653a138.zip | |
Merge pull request #804 from aguinet/feature/arm_svc
Support of ARM SVC in the Miasm VM
Diffstat (limited to 'miasm2/arch/arm/sem.py')
| -rw-r--r-- | miasm2/arch/arm/sem.py | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/miasm2/arch/arm/sem.py b/miasm2/arch/arm/sem.py index 00250157..d9c2d6cd 100644 --- a/miasm2/arch/arm/sem.py +++ b/miasm2/arch/arm/sem.py @@ -3,7 +3,7 @@ from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.arch.arm.arch import mn_arm, mn_armt from miasm2.arch.arm.regs import * -from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO +from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO, EXCEPT_INT_XX # liris.cnrs.fr/~mmrissa/lib/exe/fetch.php?media=armv7-a-r-manual.pdf EXCEPT_SOFT_BP = (1 << 1) @@ -805,9 +805,10 @@ def stmdb(ir, instr, a, b): def svc(ir, instr, a): - # XXX TODO implement - e = [ - ExprAff(exception_flags, ExprInt(EXCEPT_PRIV_INSN, 32))] + e = [] + except_int = EXCEPT_INT_XX + e.append(ExprAff(exception_flags, ExprInt(except_int, 32))) + e.append(ExprAff(interrupt_num, a)) return e, [] |