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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-02-14 17:46:38 +0100 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2017-03-13 14:10:35 +0100 |
| commit | 73828c4be50c21eae080d0e2150093a8641baab0 (patch) | |
| tree | 023ffea903e9aaddfc24409682cc47ae3d45d88d /miasm2/arch/mips32/ira.py | |
| parent | b9c87b0e9167940fbbadf0f642e07ee9d7a678e5 (diff) | |
| download | miasm-73828c4be50c21eae080d0e2150093a8641baab0.tar.gz miasm-73828c4be50c21eae080d0e2150093a8641baab0.zip | |
IR/ir: rename ir to IntermediateRepresentation
Diffstat (limited to 'miasm2/arch/mips32/ira.py')
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index 6efbf8ae..67c5f2dc 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -1,7 +1,7 @@ #-*- coding:utf-8 -*- from miasm2.expression.expression import * -from miasm2.ir.ir import ir, IRBlock, AssignBlock +from miasm2.ir.ir import IntermediateRepresentation, IRBlock, AssignBlock from miasm2.ir.analysis import ira from miasm2.arch.mips32.sem import ir_mips32l, ir_mips32b from miasm2.arch.mips32.regs import * @@ -22,7 +22,7 @@ class ir_a_mips32l(ir_mips32l, ira): return irb_cur def post_add_bloc(self, bloc, ir_blocs): - ir.post_add_bloc(self, bloc, ir_blocs) + IntermediateRepresentation.post_add_bloc(self, bloc, ir_blocs) for irb in ir_blocs: pc_val = None lr_val = None |