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| author | Ajax <commial@gmail.com> | 2018-07-02 17:31:59 +0200 |
|---|---|---|
| committer | Ajax <commial@gmail.com> | 2018-07-03 14:28:18 +0200 |
| commit | 68fac2e86cc61eba9adfe520fa0e04a7e8943450 (patch) | |
| tree | 2be74a21b54a3111f3c18746badfb0cf1ed41149 /miasm2/arch/x86/jit.py | |
| parent | 6ef8dbb2223d0847e3822b545b249511e96a1f9b (diff) | |
| download | miasm-68fac2e86cc61eba9adfe520fa0e04a7e8943450.tar.gz miasm-68fac2e86cc61eba9adfe520fa0e04a7e8943450.zip | |
symbol_pool -> loc_db
Diffstat (limited to 'miasm2/arch/x86/jit.py')
| -rw-r--r-- | miasm2/arch/x86/jit.py | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/miasm2/arch/x86/jit.py b/miasm2/arch/x86/jit.py index 5485ed85..bf74051d 100644 --- a/miasm2/arch/x86/jit.py +++ b/miasm2/arch/x86/jit.py @@ -1,10 +1,10 @@ import logging from miasm2.jitter.jitload import Jitter, named_arguments -from miasm2.core import asmblock from miasm2.core.utils import pck16, pck32, pck64, upck16, upck32, upck64 from miasm2.arch.x86.sem import ir_x86_16, ir_x86_32, ir_x86_64 from miasm2.jitter.codegen import CGen +from miasm2.core.locationdb import LocationDB from miasm2.ir.translators.C import TranslatorC log = logging.getLogger('jit_x86') @@ -18,7 +18,7 @@ class x86_32_CGen(CGen): def __init__(self, ir_arch): self.ir_arch = ir_arch self.PC = self.ir_arch.arch.regs.RIP - self.translator = TranslatorC(self.ir_arch.symbol_pool) + self.translator = TranslatorC(self.ir_arch.loc_db) self.init_arch_C() def gen_post_code(self, attrib): @@ -39,7 +39,7 @@ class jitter_x86_16(Jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_x86_16(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -71,7 +71,7 @@ class jitter_x86_32(Jitter): C_Gen = x86_32_CGen def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_x86_32(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False @@ -187,7 +187,7 @@ class jitter_x86_64(Jitter): args_regs_stdcall = ['RCX', 'RDX', 'R8', 'R9'] def __init__(self, *args, **kwargs): - sp = asmblock.AsmSymbolPool() + sp = LocationDB() Jitter.__init__(self, ir_x86_64(sp), *args, **kwargs) self.vm.set_little_endian() self.ir_arch.do_stk_segm = False |