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| author | serpilliere <fabrice.desclaux@cea.fr> | 2015-10-19 21:07:38 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-10-23 10:53:51 +0200 |
| commit | 48aa21f8adc4130750bc6b8f5da19fbe8b2cca64 (patch) | |
| tree | 6707beccac22b70e374e15b55479f1977ea05617 /miasm2/expression/expression.py | |
| parent | 09baf835bd20c6db97724d08411b23389af3860a (diff) | |
| download | miasm-48aa21f8adc4130750bc6b8f5da19fbe8b2cca64.tar.gz miasm-48aa21f8adc4130750bc6b8f5da19fbe8b2cca64.zip | |
Expression/expression: fix op len sanitycheck
Diffstat (limited to 'miasm2/expression/expression.py')
| -rw-r--r-- | miasm2/expression/expression.py | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/miasm2/expression/expression.py b/miasm2/expression/expression.py index c82aec2b..5ceb17d6 100644 --- a/miasm2/expression/expression.py +++ b/miasm2/expression/expression.py @@ -745,6 +745,7 @@ class ExprOp(Expr): # Set size for special cases if self._op in [ '==', 'parity', 'fcom_c0', 'fcom_c1', 'fcom_c2', 'fcom_c3', + 'fxam_c0', 'fxam_c1', 'fxam_c2', 'fxam_c3', "access_segment_ok", "load_segment_limit_ok", "bcdadd_cf", "ucomiss_zf", "ucomiss_pf", "ucomiss_cf"]: sz = 1 @@ -760,13 +761,20 @@ class ExprOp(Expr): 'int_16_to_double', 'int_32_to_double', 'int_64_to_double', 'int_80_to_double']: sz = 64 - elif self._op in ['double_to_mem_16', 'double_to_int_16', 'double_trunc_to_int_16']: + elif self._op in ['double_to_mem_16', 'double_to_int_16', + 'float_trunc_to_int_16', 'double_trunc_to_int_16']: sz = 16 - elif self._op in ['double_to_mem_32', 'double_to_int_32', 'double_trunc_to_int_32']: + elif self._op in ['double_to_mem_32', 'double_to_int_32', + 'float_trunc_to_int_32', 'double_trunc_to_int_32', + 'double_to_float']: sz = 32 - elif self._op in ['double_to_mem_64', 'double_to_int_64', 'double_trunc_to_int_64']: + elif self._op in ['double_to_mem_64', 'double_to_int_64', + 'float_trunc_to_int_64', 'double_trunc_to_int_64', + 'float_to_double']: sz = 64 - elif self._op in ['double_to_mem_80', 'double_to_int_80', 'double_trunc_to_int_80']: + elif self._op in ['double_to_mem_80', 'double_to_int_80', + 'float_trunc_to_int_80', + 'double_trunc_to_int_80']: sz = 80 elif self._op in ['segm']: sz = self._args[1].size |