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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-04-01 15:58:29 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-04-01 23:47:37 +0200 |
| commit | 53d82c13f7da6851196e69c67841af24bcf218b2 (patch) | |
| tree | 36a74eb31953b449544dfc6eedd8e61a1be7a5eb /test/arch/arm/arch.py | |
| parent | 5a6145c5ea3a1df1e666224962dc3ba685327a12 (diff) | |
| download | miasm-53d82c13f7da6851196e69c67841af24bcf218b2.tar.gz miasm-53d82c13f7da6851196e69c67841af24bcf218b2.zip | |
Cpu: modify instructions' offset relative encoding
The assembler will automatically use instruction len in offset computation In the following instruction: 0x10: EB 02 JMP 0x14 If we assemble this instruction, the requested instruction send to the assembler engine will be: JMP +0x4 And will be encoded to: EB 02 Previously, the assembly of: JMP +0x4 was: EB 04
Diffstat (limited to 'test/arch/arm/arch.py')
| -rw-r--r-- | test/arch/arm/arch.py | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/arch/arm/arch.py b/test/arch/arm/arch.py index 19b1236e..701c45af 100644 --- a/test/arch/arm/arch.py +++ b/test/arch/arm/arch.py @@ -66,13 +66,13 @@ reg_tests_arm = [ "002094e0"), ("0003EA9C MVN R7, R2", "0270e0e1"), - ("C00CD4DC BL 0x7C", + ("C00CD4DC BL 0x84", "1F0000EB"), - ("C00CF110 BL 0xFFFFFDEC", + ("C00CF110 BL 0xFFFFFDF4", "7BFFFFEB"), - ("000829b0 BLNE 0xFFF87110", + ("000829b0 BLNE 0xFFF87118", "441cfe1b"), ("C00EC608 TEQ R4, R5", @@ -205,7 +205,7 @@ reg_tests_arm = [ ("C00CFA40 BLX R12", "3CFF2FE1"), - ("C010DE1C BLX 0x1ECCEA", + ("C010DE1C BLX 0x1ECCF2", "3AB307FB"), ("00013028 MOV R9, 0x6E75", @@ -217,7 +217,7 @@ reg_tests_arm = [ ("0004A38C CLZ R3, R2", "123F6FE1"), - ("C0132564 BLX 0xFFFCF06C", + ("C0132564 BLX 0xFFFCF074", "1B3CFFFA"), ("C0297028 QADD R7, R6, R6", @@ -414,15 +414,15 @@ reg_tests_armt = [ ("000a1c16 STMIA R6!, {R0-R3}", "0fc6"), - ("0006af78 BEQ 0x6", + ("0006af78 BEQ 0xA", "03d0"), - ("000747b4 BCC 0xFFFFFFE6", + ("000747b4 BCC 0xFFFFFFEA", "f3d3"), # swi - ("0007479c B 0xE", + ("0007479c B 0x12", "07e0"), - ("0006b946 B 0xFFFFFFE4", + ("0006b946 B 0xFFFFFFE8", "f2e7"), ("C010163C BLX 0x1F916C", "F9F1B6E8"), |