diff options
| author | Guillaume Valadon <guillaume@valadon.net> | 2018-06-15 12:10:10 +0200 |
|---|---|---|
| committer | Guillaume Valadon <guillaume@valadon.net> | 2018-07-12 22:50:51 +0200 |
| commit | b8e5038798b0dece628846acb5ad25d9d4e60395 (patch) | |
| tree | 932dd2676afcf0c4ba6bf0c57d3b574954461ad2 /test/arch/mep/ir/test_divide.py | |
| parent | 82eb5f6eb197fc59d2e9ae21cfda05a1868e462e (diff) | |
| download | miasm-b8e5038798b0dece628846acb5ad25d9d4e60395.tar.gz miasm-b8e5038798b0dece628846acb5ad25d9d4e60395.zip | |
Toshiba MeP support
Diffstat (limited to 'test/arch/mep/ir/test_divide.py')
| -rw-r--r-- | test/arch/mep/ir/test_divide.py | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/test/arch/mep/ir/test_divide.py b/test/arch/mep/ir/test_divide.py new file mode 100644 index 00000000..04d5f6c5 --- /dev/null +++ b/test/arch/mep/ir/test_divide.py @@ -0,0 +1,99 @@ +# Toshiba MeP-c4 - Divide instructions unit tests +# Guillaume Valadon <guillaume@valadon.net> + +from ut_helpers_ir import exec_instruction + +from miasm2.expression.expression import ExprId, ExprInt, ExprCond, ExprOp +from miasm2.jitter.csts import EXCEPT_DIV_BY_ZERO + + +class TestDivide: + + def test_div(self): + """Test DIV execution""" + + # DIV Rn,Rm + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x0, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32)), + (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))]) + + # Negative numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-4, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(2, 32))]) + + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-5, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprInt(1, 32)), + (ExprId("LO", 32), ExprInt(2, 32))]) + + # Positive numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(4, 32)), + (ExprId("R1", 32), ExprInt(2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", + ExprInt(0, 32), + ExprInt(0x80000000, 32)), + ExprInt(0, 32), + ExprInt(0xFFFFFFFC, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", + ExprInt(0, 32), + ExprInt(0x80000000, 32)), + ExprInt(2, 32), + ExprInt(0, 32)))]) + + # Negative & positive numbers + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(-5, 32)), + (ExprId("R1", 32), ExprInt(2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(1, 32), ExprInt(0xFFFFFFFF, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(0x7FFFFFFD, 32), ExprInt(0xFFFFFFFE, 32)))]) + + exec_instruction("DIV R0, R1", + [(ExprId("R0", 32), ExprInt(5, 32)), + (ExprId("R1", 32), ExprInt(-2, 32))], + [(ExprId("HI", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(5, 32), ExprInt(0xFFFFFFFF, 32))), + (ExprId("LO", 32), ExprCond(ExprOp("==", ExprInt(0, 32), ExprInt(0x80000000, 32)), + ExprInt(0, 32), ExprInt(0xFFFFFFFE, 32)))]) + + def test_divu(self): + """Test DIVU execution""" + + # DIVU Rn,Rm + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x0, 32)), + (ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32))], + [(ExprId("HI", 32), ExprInt(0, 32)), + (ExprId("LO", 32), ExprInt(0, 32)), + (ExprId("exception_flags", 32), ExprInt(EXCEPT_DIV_BY_ZERO, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80, 32)), + (ExprId("R1", 32), ExprInt(0x2, 32))], + [(ExprId("HI", 32), ExprInt(0x0, 32)), + (ExprId("LO", 32), ExprInt(0x40, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x83, 32)), + (ExprId("R1", 32), ExprInt(0x2, 32))], + [(ExprId("HI", 32), ExprInt(0x1, 32)), + (ExprId("LO", 32), ExprInt(0x41, 32))]) + + exec_instruction("DIVU R0, R1", + [(ExprId("R0", 32), ExprInt(0x80000000, 32)), + (ExprId("R1", 32), ExprInt(-1, 32))], + [(ExprId("HI", 32), ExprInt(0x80000000, 32)), + (ExprId("LO", 32), ExprInt(0x0, 32))]) |