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| author | serpilliere <fabrice.desclaux@cea.fr> | 2015-10-18 01:40:26 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2015-10-23 10:47:24 +0200 |
| commit | c92d6b342bf2ff7ab569ba3851a9a23c8862befc (patch) | |
| tree | 7d4224ea301444656ade00e8135553c79a821c84 /test/arch | |
| parent | 96cbc91efb2b6918c2f13b9163789374dc412ad8 (diff) | |
| download | miasm-c92d6b342bf2ff7ab569ba3851a9a23c8862befc.tar.gz miasm-c92d6b342bf2ff7ab569ba3851a9a23c8862befc.zip | |
Test/Arch/x86:: add cvt
Diffstat (limited to 'test/arch')
| -rw-r--r-- | test/arch/x86/arch.py | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/test/arch/x86/arch.py b/test/arch/x86/arch.py index 4f6fef22..5216b3ae 100644 --- a/test/arch/x86/arch.py +++ b/test/arch/x86/arch.py @@ -2248,10 +2248,56 @@ reg_tests = [ (m32, "00000000 MAXSS XMM0, DWORD PTR [EBX+0x2CBD37]", "f30f5f8337bd2c00"), + (m32, "00000000 CVTDQ2PD XMM0, XMM3", + "f30fe6c3"), + (m32, "00000000 CVTDQ2PS XMM0, XMM3", + "0f5bc3"), + (m32, "00000000 CVTPD2DQ XMM0, XMM3", + "f20fe6c3"), + (m32, "00000000 CVTPD2PI MM0, XMM3", + "660f2dc3"), + (m32, "00000000 CVTPD2PS XMM0, XMM3", + "660f5ac3"), + (m32, "00000000 CVTPI2PD XMM0, MM3", + "660f2ac3"), + (m32, "00000000 CVTPI2PS XMM0, MM3", + "0f2ac3"), + (m32, "00000000 CVTPS2DQ XMM0, XMM3", + "660f5bc3"), + (m32, "00000000 CVTPS2PD XMM0, XMM3", + "0f5ac3"), + (m32, "00000000 CVTPS2PI MM0, XMM3", + "0f2dc3"), + (m32, "00000000 CVTSD2SI EAX, XMM3", + "f20f2dc3"), + (m32, "00000000 CVTSD2SS XMM0, XMM3", + "f20f5ac3"), (m32, "00000000 CVTSI2SD XMM0, EBX", "f20f2ac3"), (m32, "00000000 CVTSI2SS XMM0, EBX", "f30f2ac3"), + (m32, "00000000 CVTSS2SD XMM0, XMM0", + "f30f5ac0"), + (m32, "00000000 CVTSS2SI EAX, XMM3", + "f30f2dc3"), + (m32, "00000000 CVTTPD2PI MM0, XMM3", + "660f2cc3"), + (m32, "00000000 CVTTPD2DQ XMM0, XMM3", + "660fe6c3"), + (m32, "00000000 CVTTPS2DQ XMM0, XMM3", + "f30f5bc3"), + (m32, "00000000 CVTTPS2PI MM0, XMM3", + "0f2cc3"), + (m32, "00000000 CVTTSD2SI EAX, XMM3", + "f20f2cc3"), + (m32, "00000000 CVTTSS2SI EAX, XMM3", + "f30f2cc3"), + + + + + (m32, "00000000 CVTSI2SD XMM0, EBX", + "f20f2ac3"), (m32, "00000000 PMINSW MM0, MM1", "0feac1"), @@ -2456,8 +2502,6 @@ reg_tests = [ ## # SSE - (m32, "00000000 CVTSS2SD XMM0, XMM0", - "f30f5ac0"), (m32, "00000000 CVTSS2SD XMM0, DWORD PTR [EBP+0xFFFFFFD0]", "f30f5a45d0"), |