diff options
Diffstat (limited to 'miasm2')
| -rw-r--r-- | miasm2/analysis/cst_propag.py | 4 | ||||
| -rw-r--r-- | miasm2/analysis/data_analysis.py | 6 | ||||
| -rw-r--r-- | miasm2/analysis/data_flow.py | 89 | ||||
| -rw-r--r-- | miasm2/analysis/depgraph.py | 10 | ||||
| -rw-r--r-- | miasm2/analysis/disasm_cb.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/aarch64/sem.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/mips32/ira.py | 2 | ||||
| -rw-r--r-- | miasm2/arch/mips32/jit.py | 4 | ||||
| -rw-r--r-- | miasm2/arch/x86/sem.py | 2 | ||||
| -rw-r--r-- | miasm2/ir/ir.py | 73 | ||||
| -rw-r--r-- | miasm2/ir/symbexec.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/codegen.py | 4 | ||||
| -rw-r--r-- | miasm2/jitter/jitcore_python.py | 2 | ||||
| -rw-r--r-- | miasm2/jitter/llvmconvert.py | 2 |
14 files changed, 116 insertions, 92 deletions
diff --git a/miasm2/analysis/cst_propag.py b/miasm2/analysis/cst_propag.py index 2a439ccc..7946a496 100644 --- a/miasm2/analysis/cst_propag.py +++ b/miasm2/analysis/cst_propag.py @@ -73,7 +73,7 @@ class SymbExecStateFix(SymbolicExecutionEngine): self.cst_propag_link = cst_propag_link def propag_expr_cst(self, expr): - """Propagate consttant expressions in @expr + """Propagate constant expressions in @expr @expr: Expression to update""" elements = expr.get_r(mem_read=True) to_propag = {} @@ -93,7 +93,7 @@ class SymbExecStateFix(SymbolicExecutionEngine): @step: display intermediate steps """ assignblks = [] - for index, assignblk in enumerate(irb.irs): + for index, assignblk in enumerate(irb): new_assignblk = {} links = {} for dst, src in assignblk.iteritems(): diff --git a/miasm2/analysis/data_analysis.py b/miasm2/analysis/data_analysis.py index b3e15ca6..130d45a4 100644 --- a/miasm2/analysis/data_analysis.py +++ b/miasm2/analysis/data_analysis.py @@ -14,7 +14,7 @@ def intra_block_flow_raw(ir_arch, flow_graph, irb, in_nodes, out_nodes): Create data flow for an irbloc using raw IR expressions """ current_nodes = {} - for i, assignblk in enumerate(irb.irs): + for i, assignblk in enumerate(irb): dict_rw = assignblk.get_rw(cst_read=True) if irb.label.offset == 0x13: print irb.label @@ -85,7 +85,7 @@ def intra_block_flow_symbexec(ir_arch, flow_graph, irb, in_nodes, out_nodes): continue read_values = v.get_r(cst_read=True) # print n_w, v, [str(x) for x in read_values] - node_n_w = get_node_name(irb.label, len(irb.irs), n_w) + node_n_w = get_node_name(irb.label, len(irb), n_w) for n_r in read_values: if n_r in current_nodes: @@ -171,7 +171,7 @@ def create_implicit_flow(ir_arch, flow_graph, irb_in_nodes, irb_out_ndes): # print "###", irb_son # print "###", 'IN', [str(x) for x in irb_son.in_nodes] - node_n_w = irb.label, len(irb.irs), n_r + node_n_w = irb.label, len(irb), n_r irb_out_nodes[irb.label][n_r] = node_n_w if not n_r in irb_in_nodes[irb.label]: irb_in_nodes[irb.label][n_r] = irb.label, 0, n_r diff --git a/miasm2/analysis/data_flow.py b/miasm2/analysis/data_flow.py index 67768264..d9f61c56 100644 --- a/miasm2/analysis/data_flow.py +++ b/miasm2/analysis/data_flow.py @@ -6,7 +6,7 @@ from miasm2.ir.ir import AssignBlock, IRBlock class ReachingDefinitions(dict): """ - Computes for each instruction the set of reaching definitions. + Computes for each assignblock the set of reaching definitions. Example: IR block: lbl0: @@ -26,7 +26,7 @@ class ReachingDefinitions(dict): IBM Thomas J. Watson Research Division, Algorithm MK This class is usable as a dictionnary whose struture is - { (block, instr_index): { lvalue: set((block, instr_index)) } } + { (block, index): { lvalue: set((block, index)) } } """ ir_a = None @@ -36,12 +36,12 @@ class ReachingDefinitions(dict): self.ir_a = ir_a self.compute() - def get_definitions(self, block_lbl, instruction): - """Returns the dict { lvalue: set((def_block_lbl, def_instr_index)) } - associated with self.ir_a.@block.irs[@instruction] + def get_definitions(self, block_lbl, assignblk_index): + """Returns the dict { lvalue: set((def_block_lbl, def_index)) } + associated with self.ir_a.@block.assignblks[@assignblk_index] or {} if it is not yet computed """ - return self.get((block_lbl, instruction), {}) + return self.get((block_lbl, assignblk_index), {}) def compute(self): """This is the main fixpoint""" @@ -54,12 +54,12 @@ class ReachingDefinitions(dict): def process_block(self, block): """ Fetch reach definitions from predecessors and propagate it to - the instruction in block @block. + the assignblk in block @block. """ predecessor_state = {} for pred_lbl in self.ir_a.graph.predecessors(block.label): pred = self.ir_a.blocks[pred_lbl] - for lval, definitions in self.get_definitions(pred_lbl, len(pred.irs)).iteritems(): + for lval, definitions in self.get_definitions(pred_lbl, len(pred)).iteritems(): predecessor_state.setdefault(lval, set()).update(definitions) modified = self.get((block.label, 0)) != predecessor_state @@ -67,33 +67,33 @@ class ReachingDefinitions(dict): return False self[(block.label, 0)] = predecessor_state - for instr_index in xrange(len(block.irs)): - modified |= self.process_instruction(block, instr_index) + for index in xrange(len(block)): + modified |= self.process_assignblock(block, index) return modified - def process_instruction(self, block, instr_index): + def process_assignblock(self, block, assignblk_index): """ Updates the reach definitions with values defined at - instruction @instr_index in block @block. - NB: the effect of instruction @instr_index in stored at index - (@block, @instr_index + 1). + assignblock @assignblk_index in block @block. + NB: the effect of assignblock @assignblk_index in stored at index + (@block, @assignblk_index + 1). """ - instr = block.irs[instr_index] - defs = self.get_definitions(block.label, instr_index).copy() - for lval in instr: - defs.update({lval: set([(block.label, instr_index)])}) + assignblk = block[assignblk_index] + defs = self.get_definitions(block.label, assignblk_index).copy() + for lval in assignblk: + defs.update({lval: set([(block.label, assignblk_index)])}) - modified = self.get((block.label, instr_index + 1)) != defs + modified = self.get((block.label, assignblk_index + 1)) != defs if modified: - self[(block.label, instr_index + 1)] = defs + self[(block.label, assignblk_index + 1)] = defs return modified ATTR_DEP = {"color" : "black", "_type" : "data"} -InstrNode = namedtuple('InstructionNode', ['label', 'index', 'var']) +AssignblkNode = namedtuple('AssignblkNode', ['label', 'index', 'var']) class DiGraphDefUse(DiGraph): """Representation of a Use-Definition graph as defined by @@ -148,18 +148,18 @@ class DiGraphDefUse(DiGraph): deref_mem=deref_mem) def _compute_def_use_block(self, block, reaching_defs, deref_mem=False): - for ind, instr in enumerate(block.irs): - instruction_reaching_defs = reaching_defs.get_definitions(block.label, ind) - for lval, expr in instr.iteritems(): - self.add_node(InstrNode(block.label, ind, lval)) + for index, assignblk in enumerate(block): + assignblk_reaching_defs = reaching_defs.get_definitions(block.label, index) + for lval, expr in assignblk.iteritems(): + self.add_node(AssignblkNode(block.label, index, lval)) read_vars = expr.get_r(mem_read=deref_mem) if deref_mem and lval.is_mem(): read_vars.update(lval.arg.get_r(mem_read=deref_mem)) for read_var in read_vars: - for reach in instruction_reaching_defs.get(read_var, set()): - self.add_data_edge(InstrNode(reach[0], reach[1], read_var), - InstrNode(block.label, ind, lval)) + for reach in assignblk_reaching_defs.get(read_var, set()): + self.add_data_edge(AssignblkNode(reach[0], reach[1], read_var), + AssignblkNode(block.label, index, lval)) def del_edge(self, src, dst): super(DiGraphDefUse, self).del_edge(src, dst) @@ -178,25 +178,25 @@ class DiGraphDefUse(DiGraph): self.add_uniq_labeled_edge(src, dst, ATTR_DEP) def node2lines(self, node): - lbl, ind, reg = node - yield self.DotCellDescription(text="%s (%s)" % (lbl, ind), + lbl, index, reg = node + yield self.DotCellDescription(text="%s (%s)" % (lbl, index), attr={'align': 'center', 'colspan': 2, 'bgcolor': 'grey'}) - src = self._blocks[lbl].irs[ind][reg] + src = self._blocks[lbl][index][reg] line = "%s = %s" % (reg, src) yield self.DotCellDescription(text=line, attr={}) yield self.DotCellDescription(text="", attr={}) -def dead_simp_useful_instrs(defuse, reaching_defs): +def dead_simp_useful_assignblks(defuse, reaching_defs): """Mark useful statements using previous reach analysis and defuse Source : Kennedy, K. (1979). A survey of data flow analysis techniques. IBM Thomas J. Watson Research Division, Algorithm MK - Return a set of triplets (block, instruction number, instruction) of - useful instructions + Return a set of triplets (block, assignblk number, lvalue) of + useful definitions PRE: compute_reach(self) """ @@ -215,20 +215,20 @@ def dead_simp_useful_instrs(defuse, reaching_defs): # Block has a nonexistant successor or is a leaf if keep_all_definitions or (len(successors) == 0): valid_definitions = reaching_defs.get_definitions(block_lbl, - len(block.irs)) + len(block)) for lval, definitions in valid_definitions.iteritems(): if (lval in ir_a.get_out_regs(block) or keep_all_definitions): for definition in definitions: - useful.add(InstrNode(definition[0], definition[1], lval)) + useful.add(AssignblkNode(definition[0], definition[1], lval)) # Force keeping of specific cases - for instr_index, instr in enumerate(block.irs): - for lval, rval in instr.iteritems(): + for index, assignblk in enumerate(block): + for lval, rval in assignblk.iteritems(): if (lval.is_mem() or ir_a.IRDst == lval or rval.is_function_call()): - useful.add(InstrNode(block_lbl, instr_index, lval)) + useful.add(AssignblkNode(block_lbl, index, lval)) # Useful nodes dependencies for node in useful: @@ -237,22 +237,27 @@ def dead_simp_useful_instrs(defuse, reaching_defs): def dead_simp(ir_a): """ + Remove useless affectations. + This function is used to analyse relation of a * complete function * This means the blocks under study represent a solid full function graph. Source : Kennedy, K. (1979). A survey of data flow analysis techniques. IBM Thomas J. Watson Research Division, page 43 + + @ir_a: IntermediateRepresentation instance """ + modified = False reaching_defs = ReachingDefinitions(ir_a) defuse = DiGraphDefUse(reaching_defs, deref_mem=True) - useful = set(dead_simp_useful_instrs(defuse, reaching_defs)) + useful = set(dead_simp_useful_assignblks(defuse, reaching_defs)) for block in ir_a.blocks.itervalues(): irs = [] - for idx, assignblk in enumerate(block.irs): + for idx, assignblk in enumerate(block): new_assignblk = dict(assignblk) for lval in assignblk: - if InstrNode(block.label, idx, lval) not in useful: + if AssignblkNode(block.label, idx, lval) not in useful: del new_assignblk[lval] modified = True irs.append(AssignBlock(new_assignblk, assignblk.instr)) diff --git a/miasm2/analysis/depgraph.py b/miasm2/analysis/depgraph.py index d1ac13c8..bd4bfa7e 100644 --- a/miasm2/analysis/depgraph.py +++ b/miasm2/analysis/depgraph.py @@ -265,9 +265,9 @@ class DependencyResult(DependencyState): break assignmnts = {} for element in elements: - if element in irb.irs[line_nb]: + if element in irb[line_nb]: # constants, label, ... are not in destination - assignmnts[element] = irb.irs[line_nb][element] + assignmnts[element] = irb[line_nb][element] assignblks.append(AssignBlock(assignmnts)) return IRBlock(irb.label, assignblks) @@ -294,7 +294,7 @@ class DependencyResult(DependencyState): else: line_nb = None assignblks += self.irblock_slice(self._ira.blocks[label], - line_nb).irs + line_nb).assignblks # Eval the block temp_label = AsmLabel("Temp") @@ -581,9 +581,9 @@ class DependencyGraph(object): @state: instance of DependencyState""" irb = self._ira.blocks[state.label] - line_nb = len(irb.irs) if state.line_nb is None else state.line_nb + line_nb = len(irb) if state.line_nb is None else state.line_nb - for cur_line_nb, assignblk in reversed(list(enumerate(irb.irs[:line_nb]))): + for cur_line_nb, assignblk in reversed(list(enumerate(irb[:line_nb]))): self._track_exprs(state, assignblk, cur_line_nb) def get(self, label, elements, line_nb, heads): diff --git a/miasm2/analysis/disasm_cb.py b/miasm2/analysis/disasm_cb.py index 9a75603f..e759e313 100644 --- a/miasm2/analysis/disasm_cb.py +++ b/miasm2/analysis/disasm_cb.py @@ -39,7 +39,7 @@ def arm_guess_subcall( # print irblock pc_val = None lr_val = None - for exprs in irblock.irs: + for exprs in irblock: for e in exprs: if e.dst == ir_arch.pc: pc_val = e.src @@ -84,7 +84,7 @@ def arm_guess_jump_table( # print irblock pc_val = None # lr_val = None - for exprs in irblock.irs: + for exprs in irblock: for e in exprs: if e.dst == ir_arch.pc: pc_val = e.src diff --git a/miasm2/arch/aarch64/sem.py b/miasm2/arch/aarch64/sem.py index d8dc1efa..a575c819 100644 --- a/miasm2/arch/aarch64/sem.py +++ b/miasm2/arch/aarch64/sem.py @@ -827,7 +827,7 @@ class ir_aarch64l(IntermediateRepresentation): def irbloc_fix_regs_for_mode(self, irblock, mode=64): irs = [] - for assignblk in irblock.irs: + for assignblk in irblock: new_assignblk = dict(assignblk) for dst, src in assignblk.iteritems(): del(new_assignblk[dst]) @@ -870,7 +870,7 @@ class ir_aarch64l(IntermediateRepresentation): new_irblocks = [] for irblock in extra_ir: irs = [] - for assignblk in irblock.irs: + for assignblk in irblock: new_dsts = {dst:src for dst, src in assignblk.iteritems() if dst not in regs_to_fix} irs.append(AssignBlock(new_dsts, assignblk.instr)) diff --git a/miasm2/arch/mips32/ira.py b/miasm2/arch/mips32/ira.py index f1e21a41..7aefad32 100644 --- a/miasm2/arch/mips32/ira.py +++ b/miasm2/arch/mips32/ira.py @@ -21,7 +21,7 @@ class ir_a_mips32l(ir_mips32l, ira): for irb in ir_blocks: pc_val = None lr_val = None - for assignblk in irb.irs: + for assignblk in irb: pc_val = assignblk.get(self.arch.regs.PC, pc_val) lr_val = assignblk.get(self.arch.regs.RA, lr_val) diff --git a/miasm2/arch/mips32/jit.py b/miasm2/arch/mips32/jit.py index 493da595..f3e54a7d 100644 --- a/miasm2/arch/mips32/jit.py +++ b/miasm2/arch/mips32/jit.py @@ -42,12 +42,12 @@ class mipsCGen(CGen): irblocks_list = super(mipsCGen, self).block2assignblks(block) for irblocks in irblocks_list: for blk_idx, irblock in enumerate(irblocks): - has_breakflow = any(assignblock.instr.breakflow() for assignblock in irblock.irs) + has_breakflow = any(assignblock.instr.breakflow() for assignblock in irblock) if not has_breakflow: continue irs = [] - for assignblock in irblock.irs: + for assignblock in irblock: if self.ir_arch.pc not in assignblock: irs.append(AssignBlock(assignments, assignblock.instr)) continue diff --git a/miasm2/arch/x86/sem.py b/miasm2/arch/x86/sem.py index deebba8c..3cbf5526 100644 --- a/miasm2/arch/x86/sem.py +++ b/miasm2/arch/x86/sem.py @@ -4793,7 +4793,7 @@ class ir_x86_16(IntermediateRepresentation): def irbloc_fix_regs_for_mode(self, irblock, mode=64): irs = [] - for assignblk in irblock.irs: + for assignblk in irblock: new_assignblk = dict(assignblk) for dst, src in assignblk.iteritems(): del new_assignblk[dst] diff --git a/miasm2/ir/ir.py b/miasm2/ir/ir.py index afb6b382..f31db76b 100644 --- a/miasm2/ir/ir.py +++ b/miasm2/ir/ir.py @@ -258,25 +258,43 @@ class IRBlock(object): Stand for an intermediate representation basic block. """ - __slots__ = ["label", "_assignments", "_dst", "_dst_linenb"] + __slots__ = ["label", "_assignblks", "_dst", "_dst_linenb"] - def __init__(self, label, irs): + def __init__(self, label, assignblks): """ @label: AsmLabel of the IR basic block - @irs: list of AssignBlock + @assignblks: list of AssignBlock """ assert isinstance(label, AsmLabel) self.label = label - for assignblk in irs: + for assignblk in assignblks: assert isinstance(assignblk, AssignBlock) - self._assignments = tuple(irs) + self._assignblks = tuple(assignblks) self._dst = None self._dst_linenb = None + + @property + def assignblks(self): + return self._assignblks + @property def irs(self): - return self._assignments + warnings.warn('DEPRECATION WARNING: use "irblock.assignblks" instead of "irblock.irs"') + return self._assignblks + + def __iter__(self): + """Iterate on assignblks""" + return self._assignblks.__iter__() + + def __getitem__(self, index): + """Getitem on assignblks""" + return self._assignblks.__getitem__(index) + + def __len__(self): + """Length of assignblks""" + return self._assignblks.__len__() def is_dst_set(self): return self._dst is not None @@ -284,7 +302,7 @@ class IRBlock(object): def cache_dst(self): final_dst = None final_linenb = None - for linenb, assignblk in enumerate(self.irs): + for linenb, assignblk in enumerate(self): for dst, src in assignblk.iteritems(): if dst.is_id("IRDst"): if final_dst is not None: @@ -306,7 +324,7 @@ class IRBlock(object): """Generate a new IRBlock with a dst (IRBlock) fixed to @value""" irs = [] dst_found = False - for assignblk in self.irs: + for assignblk in self: new_assignblk = {} for dst, src in assignblk.iteritems(): if dst.is_id("IRDst"): @@ -328,7 +346,7 @@ class IRBlock(object): def __str__(self): out = [] out.append('%s' % self.label) - for assignblk in self.irs: + for assignblk in self: for dst, src in assignblk.iteritems(): out.append('\t%s = %s' % (dst, src)) out.append("") @@ -349,7 +367,7 @@ class IRBlock(object): mod_src = lambda expr:expr assignblks = [] - for assignblk in self.irs: + for assignblk in self: new_assignblk = {} for dst, src in assignblk.iteritems(): new_assignblk[mod_dst(dst)] = mod_src(src) @@ -387,7 +405,7 @@ class DiGraphIR(DiGraph): if node not in self._blocks: yield [self.DotCellDescription(text="NOT PRESENT", attr={})] raise StopIteration - for i, assignblk in enumerate(self._blocks[node].irs): + for i, assignblk in enumerate(self._blocks[node]): for dst, src in assignblk.iteritems(): line = "%s = %s" % (dst, src) if self._dot_offset: @@ -456,7 +474,7 @@ class IntermediateRepresentation(object): ir_bloc_cur, extra_irblocks = self.get_ir(instr) for index, irb in enumerate(extra_irblocks): irs = [] - for assignblk in irb.irs: + for assignblk in irb: irs.append(AssignBlock(assignblk, instr)) extra_irblocks[index] = IRBlock(irb.label, irs) assignblk = AssignBlock(ir_bloc_cur, instr) @@ -502,7 +520,7 @@ class IntermediateRepresentation(object): def getby_offset(self, offset): out = set() for irb in self.blocks.values(): - for assignblk in irb.irs: + for assignblk in irb: instr = assignblk.instr if instr.offset <= offset < instr.offset + instr.l: out.add(irb) @@ -607,11 +625,12 @@ class IntermediateRepresentation(object): return irblock def is_pc_written(self, block): + """Return the first Assignblk of the @blockin which PC is written + @block: IRBlock instance""" all_pc = self.arch.pc.values() - for irs in block.irs: - for assignblk in irs: - if assignblk.dst in all_pc: - return assignblk + for assignblk in block: + if assignblk.dst in all_pc: + return assignblk return None def set_empty_dst_to_next(self, block, ir_blocks): @@ -625,8 +644,8 @@ class IntermediateRepresentation(object): else: dst = m2_expr.ExprId(next_lbl, self.pc.size) - assignblk = AssignBlock({self.IRDst: dst}, irblock.irs[-1].instr) - ir_blocks[index] = IRBlock(irblock.label, list(irblock.irs) + [assignblk]) + assignblk = AssignBlock({self.IRDst: dst}, irblock[-1].instr) + ir_blocks[index] = IRBlock(irblock.label, list(irblock.assignblks) + [assignblk]) def post_add_block(self, block, ir_blocks): self.set_empty_dst_to_next(block, ir_blocks) @@ -670,13 +689,13 @@ class IntermediateRepresentation(object): """ for label, block in self.blocks.iteritems(): assignblks = [] - for assignblk in block.irs: + for assignblk in block: new_assignblk = assignblk.simplify(simplifier) assignblks.append(new_assignblk) self.blocks[label] = IRBlock(label, assignblks) def replace_expr_in_ir(self, bloc, rep): - for assignblk in bloc.irs: + for assignblk in bloc: for dst, src in assignblk.items(): del assignblk[dst] assignblk[dst.replace_expr(rep)] = src.replace_expr(rep) @@ -720,7 +739,7 @@ class IntermediateRepresentation(object): todo = set([irb.dst]) done = set() - for assignblk in reversed(irb.irs): + for assignblk in reversed(irb): if not todo: break out = self._extract_dst(todo, done) @@ -762,7 +781,7 @@ class IntermediateRepresentation(object): modified = False for label, block in self.blocks.iteritems(): irs = [] - for assignblk in block.irs: + for assignblk in block: if len(assignblk): irs.append(assignblk) else: @@ -779,9 +798,9 @@ class IntermediateRepresentation(object): # Find candidates jmp_blocks = set() for block in self.blocks.itervalues(): - if len(block.irs) != 1: + if len(block) != 1: continue - assignblk = block.irs[0] + assignblk = block[0] if len(assignblk) > 1: continue assert set(assignblk.keys()) == set([self.IRDst]) @@ -860,7 +879,7 @@ class IntermediateRepresentation(object): continue # Block has one son, son has one parent => merge assignblks =[] - for assignblk in self.blocks[block].irs: + for assignblk in self.blocks[block]: if self.IRDst not in assignblk: assignblks.append(assignblk) continue @@ -870,7 +889,7 @@ class IntermediateRepresentation(object): affs[dst] = src assignblks.append(AssignBlock(affs, assignblk.instr)) - assignblks += self.blocks[son].irs + assignblks += self.blocks[son].assignblks new_block = IRBlock(block, assignblks) self.graph.discard_edge(block, son) diff --git a/miasm2/ir/symbexec.py b/miasm2/ir/symbexec.py index 593ab49a..8ecde21c 100644 --- a/miasm2/ir/symbexec.py +++ b/miasm2/ir/symbexec.py @@ -524,7 +524,7 @@ class SymbolicExecutionEngine(object): @irb: irbloc instance @step: display intermediate steps """ - for assignblk in irb.irs: + for assignblk in irb: if step: print 'Instr', assignblk.instr print 'Assignblk:' diff --git a/miasm2/jitter/codegen.py b/miasm2/jitter/codegen.py index 61a9a784..9ed55f37 100644 --- a/miasm2/jitter/codegen.py +++ b/miasm2/jitter/codegen.py @@ -489,7 +489,7 @@ class CGen(object): for irblock in irblocks: attributes = [] irblocks_attributes.append(attributes) - for assignblk in irblock.irs: + for assignblk in irblock: attrib = Attributes(log_mn, log_regs) attributes.append(attrib) self.get_caracteristics(assignblk, attrib) @@ -534,7 +534,7 @@ class CGen(object): out = [] dst2index = None - for index, assignblk in enumerate(irblock.irs): + for index, assignblk in enumerate(irblock): if index == irblock.dst_linenb: c_dst, dst2index = self.gen_assignblk_dst(irblock.dst) else: diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py index 6d954aae..a74ef7e6 100644 --- a/miasm2/jitter/jitcore_python.py +++ b/miasm2/jitter/jitcore_python.py @@ -72,7 +72,7 @@ class JitCore_Python(jitcore.JitCore): exec_engine.update_engine_from_cpu() # Execute current ir bloc - for assignblk in irb.irs: + for assignblk in irb: instr = assignblk.instr # For each new instruction (in assembly) if instr.offset not in offsets_jitted: diff --git a/miasm2/jitter/llvmconvert.py b/miasm2/jitter/llvmconvert.py index 83349781..5fa749a5 100644 --- a/miasm2/jitter/llvmconvert.py +++ b/miasm2/jitter/llvmconvert.py @@ -1138,7 +1138,7 @@ class LLVMFunction(): case_value = None instr = instr_attrib.instr - for index, assignblk in enumerate(irblock.irs): + for index, assignblk in enumerate(irblock): # Enable cache self.main_stream = True self.expr_cache = {} |