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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-21 21:21:26 +0200 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-21 21:21:26 +0200 |
| commit | 4b927bc37359dec23f67d3427fc982945f24f404 (patch) | |
| tree | 245449ef9146942dc7fffd0235b48b7e70a00bf2 /gitlab/issues/target_i386/host_missing/accel_TCG/870.toml | |
| parent | aa8bd79cec7bf6790ddb01d156c2ef2201abbaab (diff) | |
| download | qemu-analysis-4b927bc37359dec23f67d3427fc982945f24f404.tar.gz qemu-analysis-4b927bc37359dec23f67d3427fc982945f24f404.zip | |
add gitlab issues in toml format
Diffstat (limited to 'gitlab/issues/target_i386/host_missing/accel_TCG/870.toml')
| -rw-r--r-- | gitlab/issues/target_i386/host_missing/accel_TCG/870.toml | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/gitlab/issues/target_i386/host_missing/accel_TCG/870.toml b/gitlab/issues/target_i386/host_missing/accel_TCG/870.toml new file mode 100644 index 000000000..73bd81440 --- /dev/null +++ b/gitlab/issues/target_i386/host_missing/accel_TCG/870.toml @@ -0,0 +1,20 @@ +id = 870 +title = "Throws a #GP when it should throw a #SS" +state = "closed" +created_at = "2022-02-14T04:08:24.583Z" +closed_at = "2022-03-15T16:28:26.904Z" +labels = ["accel: TCG", "target: i386"] +url = "https://gitlab.com/qemu-project/qemu/-/issues/870" +host-os = "Ubuntu 20.04.3 LTS" +host-arch = "x86" +qemu-version = "QEMU emulator version 6.2.0" +guest-os = "Custom" +guest-arch = "x86" +description = """When stacks are switched as part of a 64-bit mode privilege-level change (resulting from an interrupt), IA-32e mode loads only an inner-level RSP from the TSS. If the value of rsp from tss is a non-canonical form. It will trigger #SS. But when I test it in qemu it throws #GP instead of #SS""" +reproduce = """In order to confirm that it is the #SS triggered by the non-canonical address, We can verify on a real machine. +1. Set the value of the current core's `TSS.IST7` to the the non-canonical address. +2. Set the `ist` field of the interrupt 4 (Overflow Exception) descriptor to 7. +3. Execute the `INT 4` instruction in Ring 3 and it will be taken over by the #SS handler. + +Repeat the above steps in qemu this exception will be taken over by #GP""" +additional = """""" |