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authorChristian Krinitsin <mail@krinitsin.com>2025-05-21 21:21:26 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-05-21 21:21:26 +0200
commit4b927bc37359dec23f67d3427fc982945f24f404 (patch)
tree245449ef9146942dc7fffd0235b48b7e70a00bf2 /gitlab/issues/target_sparc/host_missing/accel_missing/2340.toml
parentaa8bd79cec7bf6790ddb01d156c2ef2201abbaab (diff)
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add gitlab issues in toml format
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+id = 2340
+title = "SPARC fp operation INVALID  trap hangs on offending instruction."
+state = "closed"
+created_at = "2024-05-09T18:06:23.731Z"
+closed_at = "2024-09-13T14:08:37.007Z"
+labels = ["target: sparc"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2340"
+host-os = "FreeBSD"
+host-arch = "amd64"
+qemu-version = "9.0.0"
+guest-os = "SunOS (Solaris)"
+guest-arch = "SPARC32 (SS-5)"
+description = """An IEEE Invalid Operation exception is typically not enabled in programs - but if it is and an Invalid Operation occurs, a hardware TRAP should be generated which eventually becomes a SIGFPE.   However, instead, the program seems to hang on the offending instruction, never moving forward.
+
+This small C example (you'll need a C compiler) demonstrates the problem, by enabling the INValid floating-pt exception, then executing the FDTOI instruction which causes an INValid trap because the floating-pt source operand is too large for the 32-bit integer result .  The SPARC V9 manual specifies that exception should happen, so it's correct to generate the trap.   However, the program simply hangs on the FDTOI instruction instead of receiving the signal.
+
+It could be something in trap emulation that is the underlying culprit here - other possible IEEE traps (such as division-by-zero) might similarly fail?
+
+`#include <ieeefp.h>`
+
+`main()`
+
+`{` 
+
+  `double val;`
+
+  `int i;`
+
+  `fpsetmask(FP_X_INV);`
+
+  `val = 1000000000000003.0; /* Number that is too large for int */`
+
+  `printf("val is %f\\n", val);`
+
+  `i = val;`
+
+  `printf("i is %d\\n", i);`
+
+`}`"""
+reproduce = """1. Enable IEEE iNValid operation traps in the TEM in the FSR.
+2. Generate an instruction that causes an iNValid trap
+3. Instruction hangs, no SIGFPE is generated"""
+additional = "n/a"