add gitlab issues in toml format

13 files changed, 296 insertions, 0 deletions

diff --git a/gitlab/issues/target_tricore/host_missing/accel_TCG/1363.toml b/gitlab/issues/target_tricore/host_missing/accel_TCG/1363.toml
new file mode 100644
index 000000000..66e8879f5
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_TCG/1363.toml
@@ -0,0 +1,15 @@
+id = 1363
+title = "TriCore: writing to registers is not working (as it's supposed to)"
+state = "closed"
+created_at = "2022-12-12T14:25:33.473Z"
+closed_at = "2022-12-19T15:08:55.000Z"
+labels = ["Closed::Fixed", "GDB", "accel: TCG", "target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1363"
+host-os = "Windows 10"
+host-arch = "Tricore"
+qemu-version = "n/a"
+guest-os = "None; bare-metal application."
+guest-arch = "Tricore"
+description = """Reading the tricore register list from QEMU works just fine. However, writing this registers is not working as expected. It looks like the bug is on QEMU's side, since third party gdb client faces the same issues."""
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1452.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1452.toml
new file mode 100644
index 000000000..2abf5375a
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1452.toml
@@ -0,0 +1,15 @@
+id = 1452
+title = "Tricore: support for shuffle and syscall instruction"
+state = "closed"
+created_at = "2023-01-19T01:31:44.517Z"
+closed_at = "2023-06-21T20:43:35.316Z"
+labels = ["kind::Feature Request", "target: tricore", "workflow::Triaged"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1452"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1453.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1453.toml
new file mode 100644
index 000000000..ddb9951cd
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1453.toml
@@ -0,0 +1,15 @@
+id = 1453
+title = "Tricore: different definitions of pcxi register field"
+state = "closed"
+created_at = "2023-01-19T02:00:48.836Z"
+closed_at = "2023-06-08T14:47:20.149Z"
+labels = ["target: tricore", "workflow::Triaged"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1453"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1523.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1523.toml
new file mode 100644
index 000000000..5719fb1a8
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1523.toml
@@ -0,0 +1,15 @@
+id = 1523
+title = "Tricore: no interrupts emulation"
+state = "opened"
+created_at = "2023-03-01T07:56:44.100Z"
+closed_at = "n/a"
+labels = ["target: tricore", "workflow::Triaged"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1523"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1667.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1667.toml
new file mode 100644
index 000000000..fa19c4dc8
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1667.toml
@@ -0,0 +1,15 @@
+id = 1667
+title = "Tricore: missing a few TC1.6.2 instruction set"
+state = "closed"
+created_at = "2023-05-26T02:53:19.089Z"
+closed_at = "2023-10-02T21:56:36.992Z"
+labels = ["target: tricore", "workflow::Patch available"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1667"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1698.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1698.toml
new file mode 100644
index 000000000..2309a4c08
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1698.toml
@@ -0,0 +1,15 @@
+id = 1698
+title = "Global-buffer-overflow in QEMU TirCore TCG"
+state = "closed"
+created_at = "2023-06-09T09:06:15.630Z"
+closed_at = "2023-06-21T20:43:35.313Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1698"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1699.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1699.toml
new file mode 100644
index 000000000..91751e230
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1699.toml
@@ -0,0 +1,15 @@
+id = 1699
+title = "Tricore: Call instruction wrong"
+state = "closed"
+created_at = "2023-06-09T09:07:53.998Z"
+closed_at = "2023-06-21T20:43:35.395Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1699"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1700.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1700.toml
new file mode 100644
index 000000000..8b3d4bc0e
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1700.toml
@@ -0,0 +1,15 @@
+id = 1700
+title = "TriCore:  helper_ret() is not correctly restoring PSW"
+state = "closed"
+created_at = "2023-06-09T13:06:42.863Z"
+closed_at = "2023-06-21T20:43:35.375Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1700"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1774.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1774.toml
new file mode 100644
index 000000000..1f6d0d233
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1774.toml
@@ -0,0 +1,35 @@
+id = 1774
+title = "8.1-rc0 failure to build with capstone 5.0"
+state = "closed"
+created_at = "2023-07-21T03:25:12.823Z"
+closed_at = "2023-07-25T19:07:52.318Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1774"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = """Use >=capstone-5.0 dependency, try to build qemu, get this error:
+```
+/opt/homebrew/Cellar/capstone/5.0/include/capstone/tricore.h:561:3: error:
+redefinition of 'tricore_feature' as different kind of symbol
+} tricore_feature;
+  ^
+../target/tricore/cpu.h:261:19: note: previous definition is here
+static inline int tricore_feature(CPUTriCoreState *env, int feature)
+                  ^
+1 error generated.
+```
+
+The fix is trivial and it was already mentioned in the mailing list but wasn't fixed for rc0, so I figured it might have been forgotten about.
+
+https://lore.kernel.org/qemu-devel/CA+PgxXVxVKpT0SZ3N+Fc1YvXCiwkkbqm0FmLKqLTbgcDpYCNgg@mail.gmail.com/
+
+If you meet any other problem with capstone (e.g. some regression), please don't hesitate to report it mainstream.
+
+There are plans to make a new patch release soon with fixes for some most annoying bugs since the 5.0 release: https://github.com/capstone-engine/capstone/issues/2081
+
+https://github.com/capstone-engine/capstone/releases"""
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/1847.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/1847.toml
new file mode 100644
index 000000000..f229dfd6b
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/1847.toml
@@ -0,0 +1,15 @@
+id = 1847
+title = "TriCore missing ftoq31, ftoq31z, and q31tof instructions"
+state = "opened"
+created_at = "2023-08-26T16:10:12.292Z"
+closed_at = "n/a"
+labels = ["kind::Feature Request", "target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1847"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/596.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/596.toml
new file mode 100644
index 000000000..8f4228cda
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/596.toml
@@ -0,0 +1,15 @@
+id = 596
+title = "\"./ylwrap: -d: not found\" error in tricore-debian-cross-container job"
+state = "closed"
+created_at = "2021-09-03T17:32:46.569Z"
+closed_at = "2022-01-19T16:37:25.298Z"
+labels = ["Build System", "target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/596"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/652.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/652.toml
new file mode 100644
index 000000000..7c0266daf
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/652.toml
@@ -0,0 +1,40 @@
+id = 652
+title = "Tricore: wrong implementation of OPC1_16_SRO_LD_H in target/tricore/translate.c"
+state = "closed"
+created_at = "2021-09-30T16:48:32.641Z"
+closed_at = "2023-02-09T11:23:01.887Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/652"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "not needed, fail is trivial"
+guest-arch = "tricore"
+description = """The translation of the 16bit opcode LD.HD[15], A[b], off4 (SRO) is not done properly.
+Page 210 of
+https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8
+as 
+D[15] = sign_ext(M(A[b] + zero_ext(2 * off4), half-word));
+1) Implemented in target/tricore/translate.c as
+    case OPC1_16_SRO_LD_H:
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
+        break;
+
+2) Should be 
+    case OPC1_16_SRO_LD_H:
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
+        break;
+
+Detected: 
+testsuite gcc9.1.0 delta analysis of Infineon Instruction Set Simulator vs. qemu-system-tricore
+fix from 2) is successfull
+
+Confidence Level for bugfix high.
+Is according to spec. and in line with reference Instruction Set Simulator from Infineon.
+
+Motivation
+Reexecution of gcc/g++/libstdc++ testsuites with qemu
+
+I honor the implementation work which was done by bkoppelmann, vo_lumit@gmx.de"""
+reproduce = "n/a"
+additional = "n/a"
diff --git a/gitlab/issues/target_tricore/host_missing/accel_missing/653.toml b/gitlab/issues/target_tricore/host_missing/accel_missing/653.toml
new file mode 100644
index 000000000..06f5195aa
--- /dev/null
+++ b/gitlab/issues/target_tricore/host_missing/accel_missing/653.toml
@@ -0,0 +1,71 @@
+id = 653
+title = "Tricore: wrong implementation of OPC2_32_RCRW_IMASK and OPC2_32_RCRW_INSERT in target/tricore/translate.c"
+state = "closed"
+created_at = "2021-09-30T17:04:02.045Z"
+closed_at = "2023-03-03T12:15:46.945Z"
+labels = ["target: tricore"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/653"
+host-os = "n/a"
+host-arch = "n/a"
+qemu-version = "n/a"
+guest-os = "not needed, fail is trivial"
+guest-arch = "tricore"
+description = """The translation of the instructions is not done properly.
+please check
+https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8
+
+1) Implemented in target/tricore/translate.c as
+    switch (op2) {
+    case OPC2_32_RCRW_IMASK:
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
+        tcg_gen_movi_tl(temp2, (1 << width) - 1);
+        tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
+        tcg_gen_movi_tl(temp2, const4);
+        tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
+        break;
+    case OPC2_32_RCRW_INSERT:
+        temp3 = tcg_temp_new();
+
+        tcg_gen_movi_tl(temp, width);
+        tcg_gen_movi_tl(temp2, const4);
+        tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
+        gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
+
+        tcg_temp_free(temp3);
+        break;
+
+2) Should be 
+    case OPC2_32_RCRW_IMASK:
+        tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
+        tcg_gen_movi_tl(temp2, (1 << width) - 1);
+        tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
+        tcg_gen_movi_tl(temp2, const4);
+        tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
+        break;
+    case OPC2_32_RCRW_INSERT:
+        temp3 = tcg_temp_new();
+
+        tcg_gen_movi_tl(temp, width);
+        tcg_gen_movi_tl(temp2, const4);
+        tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+        gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3);
+
+        tcg_temp_free(temp3);
+        break;
+From encoding point of view d4 is target and not source.
+Assumption is here misleading swap of d3 and d4.
+
+
+Detected: 
+testsuite libstdc++ 9.1.0 delta analysis of Infineon Instruction Set Simulator vs. qemu-system-tricore
+fix from 2) is successfull
+
+Confidence Level for bugfix high.
+Is according to spec. and in line with reference Instruction Set Simulator from Infineon.
+
+Motivation
+Reexecution of gcc/g++/libstdc++ testsuites with qemu
+
+I honor the implementation work which was done by bkoppelmann, vo_lumit@gmx.de"""
+reproduce = "n/a"
+additional = "n/a"