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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
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| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-06-01 21:35:14 +0200 |
| commit | 3e4c5a6261770bced301b5e74233e7866166ea5b (patch) | |
| tree | 9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_arm/host_missing/accel_TCG/1062 | |
| parent | e5634e2806195bee44407853c4bf8776f7abfa4f (diff) | |
| download | qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.tar.gz qemu-analysis-3e4c5a6261770bced301b5e74233e7866166ea5b.zip | |
clean up repository
Diffstat (limited to 'gitlab/issues_text/target_arm/host_missing/accel_TCG/1062')
| -rw-r--r-- | gitlab/issues_text/target_arm/host_missing/accel_TCG/1062 | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/gitlab/issues_text/target_arm/host_missing/accel_TCG/1062 b/gitlab/issues_text/target_arm/host_missing/accel_TCG/1062 deleted file mode 100644 index b4a09b094..000000000 --- a/gitlab/issues_text/target_arm/host_missing/accel_TCG/1062 +++ /dev/null @@ -1,16 +0,0 @@ -AArch64: SCR_EL3.RW behaves incorrectly for CPUs with no AArch32 -Description of problem: -In the ARM DDI 0487G.a, D13-3572, the SCR_EL3.RW bit is defined as RAO/WI if both EL2 and EL1 don't support Aarch32. However, the function `scr_write` in `target/arm/helper.c` does not reflect this behavior, even though it checks for Aarch32 EL1 support. - -This would break this EL3 code, which should run on cpu reset to attempt to return to EL1: -```asm -mov x1, #((1<<0)|(1<<2)|(1<<6)|(1<<7)|(1<<8)|(1<<9)) ; EL1h, DAIF masked -mov SPSR_EL3, x1 -adr x1, 1f -msr ELR_EL3, x1 -eret -1: -; something something -``` -Additional information: - |