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authorChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-06-01 21:35:14 +0200
commit3e4c5a6261770bced301b5e74233e7866166ea5b (patch)
tree9379fddaba693ef8a045da06efee8529baa5f6f4 /gitlab/issues_text/target_riscv/host_missing/accel_TCG/2259
parente5634e2806195bee44407853c4bf8776f7abfa4f (diff)
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-The cause code of a trap changes when qemu is nested in another qemu
-Description of problem:
-I am studying the feasibility of doing some practical work on RISCV plates. Since I don't have these boards yet, I'm emulating it with qemu. The practice in turn consists of launching with qemu a very small operating system with two tasks that make a series of system calls.
-
-When I run this practice on my host it works correctly, but when I run it on an Ubuntu emulated in riscv with qemu, the cause code for the trap changes (the first bit of the code).
-
-The demo can be found in this repository: https://github.com/Sft570/qemu-bug-report
-Steps to reproduce:
-1. Clone the repository on the host and run the demo with "make qemu"
-2. Emulate with qemu ubuntu in riscv, clone the repository and run the demo with "make qemu".
-
-The error displayed shows the change of the cause code bit. You can analyze its behavior in the trap.c file in the src folder.
-Additional information:
-